Impact of Semiconductor and Interface-State Capacitance on Metal/High-k/GaAs Capacitance–Voltage Characteristics

Sonnet, A. M.; Hinkle, Christopher; Heh, D.; Bersuker, G.; Vogel, Eric M.

doi:10.1109/ted.2010.2059029

Cited by 43 publications

(31 citation statements)

References 28 publications

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“…To accurately model this response requires a revised interface trap capacitance calculation that incorporates tunneling of carriers into defect states that reside away from the crystalline semiconductor interface. Two models that include this tunneling mechanism are the disorder induced gap states (DIGS) model 34,35 and border traps. 36,37 Our current understanding of the origin of this frequency response necessitates that the defect states are associated with the disruption of the III-V interface and not with border traps located throughout the bulk of the high-k dielectric.…”

Section: Resultsmentioning

confidence: 99%

Chemical and electrical characterization of the HfO2/InAlAs interface

Brennan

Galatage

Thomas

et al. 2013

Journal of Applied Physics

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InAlAs has the potential to be used as a barrier layer in buried channel quantum well field effect transistor devices due to favorable lattice-matching and carrier confinement properties with InGaAs. Field effect device structures of this nature may also require a high-k oxide deposited on the InAlAs surface to reduce leakage current. This study investigates the impact of surface preparations and atomic layer deposition of HfO2 on these surfaces using x-ray photoelectron spectroscopy to analyse the chemical interactions taking place, as well as the electrical performance of associated capacitor devices. A large concentration of As related surface features is observed at the InAlAs surface, and is attributed to a large D-it response in electrical measurements. (C) 2013 AIP Publishing LLC

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Section: Resultsmentioning

confidence: 99%

Chemical and electrical characterization of the HfO2/InAlAs interface

Brennan

Galatage

Thomas

et al. 2013

Journal of Applied Physics

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“…The defect (trap) density (D it ) of this interface can be quite high, pinning the Fermi level and resulting in significantly degraded transport properties. 1 Recent theoretical studies 2,3 and previous experimental work 4 indicate that the suppression of particular interfacial oxidation states can reduce this D it and improve the performance of III-V based materials. Strategies such as Si (Refs.…”

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confidence: 99%

In-situ characterization of Ga2O passivation of In0.53Ga0.47As prior to high-k dielectric atomic layer deposition

Milojević

Contreras-Guerrero

O’Connor

et al. 2011

Applied Physics Letters

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Ga2O interfacial passivation layers (IPLs) on In0.53Ga0.47As are investigated using in-situ monochromatic x-ray photoelectron spectroscopy. The oxide is entirely composed of Ga2O when deposited with an effusion cell temperature of 1500 degrees C and substrate temperature of 425 degrees C. The growth on In0.53Ga0.47As reveals slight chemical modification of the surface. The Ga2O behavior and ability to protect the III-V surface are observed following Al2O3 deposition by atomic layer deposition following each precursor pulse. Al2O3 growth by trimethyl-Al (TMA) and water reveals that the IPL undergoes the "clean-up" effect following TMA exposures causing As-As bonding formation resulting in a high interface state density. (C) 2011 American Institute of Physics. (doi:10.1063/1.3615666

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“…In selecting the gate oxide, a band offset larger than 1 eV is needed to suppress leakage currents. 6 In this respect, Al 2 O 3 is an excellent high-j dielectric, due to its high permittivity (8)(9)(10), large bandgap (8.9 eV), and high energy conduction band edge offset with GaN [2.13 eV (Ref.…”

Section: Introductionmentioning

confidence: 99%

“…9 These trap states are caused by rough interfaces, incomplete and unsatisfied chemical bonds, and impurities. 10 This paper verifies the effectiveness of an ex situ wet chemical etching of GaN prior to ALD of Al 2 O 3 .…”

Section: Introductionmentioning

confidence: 99%

Effect of GaN surface treatment on Al2O3/n-GaN MOS capacitors

Hossain

Wei

Edgar

et al. 2015

Journal of Vacuum Science &Amp; Technology B, Nanotechnology and Microelectronics: Materials, Processing, Measurement, and Phen

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The surface preparation for depositing Al 2 O 3 for fabricating Au/Ni/Al 2 O 3 /n-GaN (0001) metal oxide semiconductor (MOS) capacitors was optimized as a step toward realization of high performance GaN MOSFETs. The GaN surface treatments studied included cleaning with piranha (H 2 O 2 :H 2 SO 4 ¼ 1:5), (NH 4 ) 2 S, and 30% HF etches. By several metrics, the MOS capacitor with the piranha-etched GaN had the best characteristics. It had the lowest capacitance-voltage hysteresis, the smoothest Al 2 O 3 surface as determined by atomic force microscopy (0.2 nm surface roughness), the lowest carbon concentration ($0.78%) at the Al 2 O 3 /n-GaN interface (from x-ray photoelectron spectroscopy), and the lowest oxide-trap charge (Q T ¼ 1.6 Â 10 11 cm À2 eV À1

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Impact of Semiconductor and Interface-State Capacitance on Metal/High-k/GaAs Capacitance–Voltage Characteristics

Cited by 43 publications

References 28 publications

Chemical and electrical characterization of the HfO2/InAlAs interface

Chemical and electrical characterization of the HfO2/InAlAs interface

In-situ characterization of Ga2O passivation of In0.53Ga0.47As prior to high-k dielectric atomic layer deposition

Effect of GaN surface treatment on Al2O3/n-GaN MOS capacitors

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