2014
DOI: 10.1109/tns.2014.2333542
|View full text |Cite
|
Sign up to set email alerts
|

Impact of Single Event Gate Rupture and Latent Defects on Power MOSFETs Switching Operation

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
1

Citation Types

0
1
0

Year Published

2017
2017
2023
2023

Publication Types

Select...
4
1

Relationship

0
5

Authors

Journals

citations
Cited by 5 publications
(1 citation statement)
references
References 30 publications
0
1
0
Order By: Relevance
“…Titus et al [ 13 ] reviewed the mechanism of single-event burnout (SEB) and SEGR. Privat et al [ 14 ] investigated the impact of the latent defects on SEGR during switching operations. Recently, more studies have focused on the SEGR hardening technologies, such as the thicker gate oxide at the trench bottom proposed by Ttius et al [ 3 ] and Darwish et al [ 15 ], the W-shaped gate dielectric proposed by [ 16 ], the high-k gate dielectric proposed by X. Wan et al [ 17 ] and A. Javanainen et al [ 18 ], the widened split gate proposed by Jiang Lu et al [ 19 ], the super-junction power MOS proposed by Muthuseenu et al [ 20 ], and so on.…”
Section: Introductionmentioning
confidence: 99%
“…Titus et al [ 13 ] reviewed the mechanism of single-event burnout (SEB) and SEGR. Privat et al [ 14 ] investigated the impact of the latent defects on SEGR during switching operations. Recently, more studies have focused on the SEGR hardening technologies, such as the thicker gate oxide at the trench bottom proposed by Ttius et al [ 3 ] and Darwish et al [ 15 ], the W-shaped gate dielectric proposed by [ 16 ], the high-k gate dielectric proposed by X. Wan et al [ 17 ] and A. Javanainen et al [ 18 ], the widened split gate proposed by Jiang Lu et al [ 19 ], the super-junction power MOS proposed by Muthuseenu et al [ 20 ], and so on.…”
Section: Introductionmentioning
confidence: 99%