Impact of Single-Event Upsets on Convolutional Neural Networks in Xilinx Zynq FPGAs

Wang, H.-B.; Wang, Y.-S.; Reviriego, Pedro; Wang, S.-L.; Liang, Tianjiao

doi:10.1109/tns.2021.3062014

Cited by 28 publications

(15 citation statements)

References 23 publications

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“…Closer to this work, several works have proposed methods to apply full or partial TMR to neural network accelerators. For example, Wang et al [6] implemented full TMR on a custom light-weight CNN topology. Their approach significantly improved the error rate (33.59% error rate reduction) although they incur a large increase in hardware resources.…”

Section: Related Workmentioning

confidence: 99%

“…In this work, we propose fault tolerant NN accelerators leveraging parallelism using FPGAs for acceleration (as per suggested in [3]), targeting convolutional layers (as [10]), targeting reduced hardware overhead (as per suggested in [4,6]), and applying partial TMR, as [7][8][9], but with a finer grained approach to Selective Hardening or SHIELDeNN, as we analyse and triplicate individual channels within a layer, instead of the entire layer. This work could be considered to be an extension to Gambardella et al [2], developing the ideas proposed in the work into a tool which generates reliable accelerators.…”

Section: Related Workmentioning

confidence: 99%

See 1 more Smart Citation

Fault-Tolerant Neural Network Accelerators With Selective TMR

et al. 2023

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Neural networks are a popular choice to accurately perform complex classification tasks. In edge applications, neural network inference is accelerated on embedded hardware platforms, which often utilise FPGA-based architectures, due to their low-power and flexible parallelism. A significant amount of applications require resilient hardware against faults, being compliant to safety standards. In this work, we present Selective TMR, an automated tool which analyses the sensitivity of computations within neural network inference to the overall network accuracy. The tool then triplicates the most sensitive computations, which increases the functional safety of the neural network accelerator without resorting to full triple modular redundancy (TMR). As a result, this allows designers to explore trade-off between accelerator reliability and hardware cost. In some cases, we see an improvement in 24% minimum accuracy under a single stuck@ hardware fault, while increasing the overall resource footprint by 56%.

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Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Fault-Tolerant Neural Network Accelerators With Selective TMR

et al. 2023

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show abstract

“…Except for our pioneering works ([14] [19]), this is the only work employing resource-constrained devices in the experiments. The remaining works consider FPGA implementations of ML algorithms [5][12][6] [15][17] [7] or their execution on generic graphics processing units (GPUs) [11], and ML specialised accelerators [13][16] [18]. All works, with exception of [5], adopted neutron irradiation for their experiments.…”

Section: Related Work In Machine Learning Soft Error Assessment and M...mentioning

confidence: 99%

“…Datasets are not always available and the retraining cost may not be affordable to complex accelerators or every single business case [4]. More traditional hardening approaches (e.g., triple modular redundancy -TMR) have also been either adapted for DNN solutions implemented in FPGAs [5][6] [7] or applied to DNN models running in specialised accelerators [8] [9]. However, the lower resource availability of edge-computing devices makes traditional redundancy mitigation approaches unsuitable for tackling the occurrence of radiation-induced soft errors, given their likely impact on the system's performance and response time.…”

Section: Introductionmentioning

confidence: 99%

A Lightweight Mitigation Technique for Resource- Constrained Devices Executing DNN Inference Models Under Neutron Radiation

Gava

Hanneman

Abich

et al. 2023

IEEE Trans. Nucl. Sci.

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Deep neural network (DNN) models are being deployed in safety-critical embedded devices for object identification, recognition, and even trajectory prediction. Optimised versions of such models, in particular the convolutional ones, are becoming increasingly common in resource-constrained edge-computing devices (e.g., sensors, drones), which typically rely on reduced memory footprint, low power budget and low-performance microprocessors. DNN models are prone to radiation-induced soft errors, and tackling their occurrence in resource-constrained devices is a mandatory and substantial challenge. While traditional replication-based soft error mitigation techniques will likely account for a reasonable performance penalty, hardware solutions are even more costly. To undertake this almost contradictory challenge, this work evaluates the efficiency of a lightweight software-based mitigation technique, called Register Allocation Technique (RAT), when applied to a convolutional neural network (CNN) model running on two commercial Arm microprocessors (i.e., Cortex-M4 and M7) under the effects of neutron radiation. Gathered results obtained from two neutron radiation campaigns suggest that RAT can reduce the number of critical faults in the CNN model running on both Arm Cortex-M microprocessors. Results also suggest that the SDC FIT rate of the RAT-hardened CNN model can be reduced in up to 83% with a runtime overhead of 32%.

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“…Secondly, it involves optimizing the design of CNN algorithms. In [17,18], the method of weight quantization can reduce the sensitivity of CNNs to SEUs. In [19], three modern deep convolutional CNNs were tested for their robustness.…”

Section: Introductionmentioning

confidence: 99%

Evaluation and Mitigation of Weight-Related Single Event Upsets in a Convolutional Neural Network

Cai,

et al. 2024

Electronics

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Single Event Upsets (SEUs) are most likely to cause bit flips within the trained parameters of a convolutional neural network (CNN). Therefore, it is crucial to analyze and implement hardening techniques to enhance their reliability under radiation. In this paper, random fault injections into the weights of LeNet-5 were carried out in order to evaluate and propose strategies to improve the reliability of a CNN. According to the results of an SEU fault injection, the accuracy of the CNN can be classified into the following three categories: benign conditions, poor conditions, and critical conditions. Two efficient methods for mitigating weight-related SEUs are proposed, as follows: weight limiting and Triple Modular Redundancy (TMR) for the critical bit of the critical layer. The hardening results show that when the number of SEU faults is small, the weight limiting almost completely eliminates the critical and poor conditions of LeNet-5’s accuracy. Additionally, even when the number of SEU faults is large enough, combining the weight limiting and TMR methods for the critical bit of the critical layer can retain the occurrence rate of benign conditions at 98%, saving 99.3% of the hardware resources compared to the Full-TMR hardening method.

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Impact of Single-Event Upsets on Convolutional Neural Networks in Xilinx Zynq FPGAs

Cited by 28 publications

References 23 publications

Fault-Tolerant Neural Network Accelerators With Selective TMR

Fault-Tolerant Neural Network Accelerators With Selective TMR

A Lightweight Mitigation Technique for Resource- Constrained Devices Executing DNN Inference Models Under Neutron Radiation

Evaluation and Mitigation of Weight-Related Single Event Upsets in a Convolutional Neural Network

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