2017
DOI: 10.1002/jnm.2283
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Impact of source pocket doping on RF and linearity performance of a cylindrical gate tunnel FET

Abstract: The paper presents a cylindrical gate tunnel (CGT) field effect transistors (FETs) with a highly doped pocket layer introduced in the source region. The presence of pocket doped layer in the source provides higher lateral electric field and band‐to‐band tunneling (BTBT) generation rate in the vicinity of tunneling junction which in turn increases the drain current and transconductance significantly. Also, the linearity and radio frequency (RF) performance of the CGT FET with source pocket doping (CGTS) have be… Show more

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Cited by 16 publications
(13 citation statements)
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“…Linearity and distortion analysis using different matrices such as VIP2, VIP3, IIP3, IMD3, 1‐dB compression point, HD2, HD3, and higher‐order transconductance coefficient are efficient and time‐consuming methods 16–20 . There are some advantages in cylindrical gate TFETs with a source pocket doping in terms of analog, linearity, and RF performance 21 . The effect of adding a ferroelectric layer on RF/analog and linearity analysis for the ferroelectric finFET is also studied 22 .…”
Section: Introductionmentioning
confidence: 99%
“…Linearity and distortion analysis using different matrices such as VIP2, VIP3, IIP3, IMD3, 1‐dB compression point, HD2, HD3, and higher‐order transconductance coefficient are efficient and time‐consuming methods 16–20 . There are some advantages in cylindrical gate TFETs with a source pocket doping in terms of analog, linearity, and RF performance 21 . The effect of adding a ferroelectric layer on RF/analog and linearity analysis for the ferroelectric finFET is also studied 22 .…”
Section: Introductionmentioning
confidence: 99%
“…Regardless of all these advantages, TFET is dealing with some major issues that correspond to reduced drain current, ambipolar state conduction, and deficient high-frequency performance [8][9][10][11]. Many researchers have introduced several techniques such as gate overlapping on the drain region [12], using hetero gate dielectric [13], tunneling junction engineering [14], gate work function engineering [15], and the introduction of pocket layer [16,17] to raise the ON-state current of all silicon TFETs. These approaches mainly focused on the tunneling barrier width modulation and high electric field at the junction region to enhance the drain current performance.…”
Section: Introductionmentioning
confidence: 99%
“…On the other hand, the existence of higher‐order harmonics causes the non‐linear behaviour of the device owing to the loss of information [1, 2]. Therefore, it is the primary concern to choose the device which ensures the minimal influence of inter‐modulation distortions and high‐order harmonics on the reliability of the device [3, 4]. Thus, a novel device having a lower value of subthreshold slope (normalSS) is required.…”
Section: Introductionmentioning
confidence: 99%