Impact of technology scaling and packaging on dynamic voltage scaling techniques

Duarte, D.; Vijaykrishnan, N.; Irwin, M.J.; Tsai, Yuh-Fang

doi:10.1109/asic.2002.1158064

Cited by 8 publications

(6 citation statements)

References 8 publications

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“…A five fold increase in the leakage power is predicted with each technology generation [5]. The static power consumption is comparable to the dynamic power dissipation and projected to surpass it if measures are not taken to minimize leakage current [9].…”

Section: Introductionmentioning

confidence: 89%

Leakage aware dynamic voltage scaling for real-time embedded systems

Jejurikar

Pereira

Gupta

2004

Proceedings of the 41st Annual Design Automation Conference

313

369

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A five-fold increase in leakage current is predicted with each technology generation. While Dynamic Voltage Scaling (DVS) is known to reduce dynamic power consumption, it also causes increased leakage energy drain by lengthening the interval over which a computation is carried out. Therefore, for minimization of the total energy, one needs to determine an operating point, called the critical speed. We compute processor slowdown factors based on the critical speed for energy minimization. Procrastination scheduling attempts to maximize the duration of idle intervals by keeping the processor in a sleep/shutdown state even if there are pending tasks, within the constraints imposed by performance requirements. Our simulation experiments show that the critical speed slowdown results in up to 5% energy gains over a leakage oblivious dynamic voltage scaling. Procrastination scheduling scheme extends the sleep intervals to up to 5 times, resulting in up to an additional 18% energy gains, while meeting all timing requirements.

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Section: Introductionmentioning

confidence: 89%

Leakage aware dynamic voltage scaling for real-time embedded systems

Jejurikar

Pereira

Gupta

2004

Proceedings of the 41st Annual Design Automation Conference

313

369

View full text Add to dashboard Cite

show abstract

“…In past technologies, the dynamic power was much larger than the static power. With each technology generation, however, the leakage current is predicted to increase by a factor of five [6] and the static power consumption is predicted to surpass the dynamic power consumption [7].…”

Section: Introductionmentioning

confidence: 99%

Leakage-Aware Multiprocessor Scheduling

Langen

Juurlink

2008

J Sign Process Syst Sign Image Video Technol

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When peak performance is unnecessary, Dynamic Voltage Scaling (DVS) can be used to reduce the dynamic power consumption of embedded multiprocessors. In future technologies, however, static power consumption due to leakage current is expected to increase significantly. Then it will be more effective to limit the number of processors employed (i.e., turn some of them off), or to use a combination of DVS and processor shutdown. In this paper, leakage-aware scheduling heuristics are presented that determine the best trade-off between these three techniques: DVS, processor shutdown, and finding the optimal number of processors. Experimental results obtained using a public benchmark set of task graphs and real parallel applications show that our approach reduces the total energy consumption by up to 46% for tight deadlines (1.5× the critical path length) and by up to 73% for loose deadlines (8× the critical path length) compared to an approach that only employs DVS. We also compare the energy consumed by our scheduling algorithms to two absolute lower bounds, one for the case where all processors continuously run at the same frequency, and one for the case where the processors can run at different frequencies and these frequencies may change over time. The results show that the energy reduction achieved by our best approach is close to these theoretical limits.

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“…For example, in Figure 3(b), the values of 3,1 and 3,2 are, respectively, 4 − 0 and 1 − 0 , and the values of 3,1 and 3,2 are, respectively, 3 − ( 4 − 0 ) and 7 − ( 1 − 0 ). In accordance with (4), the values of REW (3,1) and REW (3,2) are (3 − ( 4 − 0 ))/( 4 − 0 ) and (7 − ( 1 − 0 ))/( 1 − 0 ). Assuming that available slack for By updating the information of arcs in WDG during runtime, we can traverse the vertices of WDG by following the current job and make decisions on switching the processor to active or dormant mode.…”

Section: Latency Locking Pcpmentioning

confidence: 58%

“…Many previous works have addressed DVS based on performance requirements to minimize the dynamic power consumption [1][2][3][4][5][6][7][8][9][10][11][12][13]. While techniques to optimize the total static and dynamic power consumption have been proposed, they are still based on the ideal system environment without considering resource synchronization problem.…”

Section: Introductionmentioning

confidence: 99%

A Blocking-Aware Scheduling for Real-Time Task Synchronization Using a Leakage-Controlled Method

Chen

Hsieh

2014

International Journal of Distributed Sensor Networks

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Due to the importance of power dissipation in the wireless sensor networks and embedded systems, real-time scheduling has been studied in terms of various optimization problems. Real-time tasks that synchronize to enforce mutually exclusive access to the shared resources could be blocked by lower priority tasks. While dynamic voltage scaling (DVS) is known to reduce dynamic power consumption, it causes increased blocking time due to lower priority tasks that prolong the interval over which a computation is carried out. Additionally, processor slowdown to increase execution time implies greater leakage energy consumption. In this paper, a leakage-controlled method is proposed, which decreases both priority inversion and power consumption. Based on priority ceiling protocol (PCP) and a graph reduction technique, this method can decrease more energy consumption and avoid priority inversion for real-time tasks.

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Impact of technology scaling and packaging on dynamic voltage scaling techniques

Cited by 8 publications

References 8 publications

Leakage aware dynamic voltage scaling for real-time embedded systems

Leakage aware dynamic voltage scaling for real-time embedded systems

Leakage-Aware Multiprocessor Scheduling

A Blocking-Aware Scheduling for Real-Time Task Synchronization Using a Leakage-Controlled Method

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