Impact of Temperature on Analog/RF Performance of Dielectric Pocket Gate-all-around (DPGAA) MOSFETs

Awasthi, Himanshi; Kumar, Nitish; Purwar, Vaibhav; Gupta, Rajeev; Dubey, Sarvesh

doi:10.1007/s12633-020-00610-2

Cited by 16 publications

(6 citation statements)

References 15 publications

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“…Remarkable n-JLSDGM's features such as ultrathin and fully depleted body would minimize the parasitic capacitances between regions. Hence, it is crucial to ensure the magnitude of C gg as well as P dyn to be as low as possible in maintaining an ideal temperature for the RF circuits [36]. Any significant rise in temperature could deteriorate the device performance either in on-state or off-state.…”

Section: Rf Performancesmentioning

confidence: 99%

Work function variations on electrostatic and RF performances of JLSDGM Device

Kaharudin

Salehuddin²,

Zain³

et al. 2021

IJEECS

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This paper offers a systematic analysis on the impact of work function (WF) variations on electrostatic and radio frequency (RF) performances of nchannel junctionless strained double gate (DG) (n-JLSDGM) metal oxide semiconductor field effect transistor (MOSFET). The study has been performed under othe constant level of design parameters that operates in saturation as a transconductance amplifier, considering the dependence of electrostatic and RF performance on the variation of WF. Furthermore, this paper aims to provide physical insight into the improved electrostatic and RF performances of the proposed n-JLSDGM device. The device layout and characteristics were designed and extracted respectively via a comprehensive 2-D simulation. Device performances such as on-state current (ION), off-state current (IOFF), on-off current ratio, subthreshold swing (SS), intrinsic capacitances, dynamic power dissipation (Pdyn), cut-off frequency (fT) and maximum oscillation frequency (fmax) are intensively investigated in conjunction with WF variations.

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Section: Rf Performancesmentioning

confidence: 99%

Work function variations on electrostatic and RF performances of JLSDGM Device

Kaharudin

Salehuddin²,

Zain³

et al. 2021

IJEECS

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“…Multigate devices [1][2][3][4][5][6] designs like FinFET, Omega FET, and gate-all-around (GAA) are analyzed over different parameters. The GAA MOSFET [6,7] is becoming a cornerstone due to multidirectional electrostatic control over the gate, superior SCE immunity, and high packing density. In smaller-scaled devices, if the voltage at the drain is expanded, the potential barrier in the channel minimizes, which indicates that the gate loses its control over the channel, overseeing drain-induced barrier lowering (DIBL).…”

Section: Introductionmentioning

confidence: 99%

Comparative Study of Silicon and In0.53Ga0.47As-Based Gate-All-Around (GAA) MOSFETs

Awasthi

Kumar

Purwar³

et al. 2021

Lecture Notes in Electrical Engineering

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“…This modified MOS structure is also known as an insulated-shallow extension (I SE) version of MOS [9]. Incorporation of D P is used to prevent the SC Es and reduce the leakage or O F F-current (I OFF ) [9][10][11][12]. D P is also termed as a diffusion stopper incorporated in the channel from the source and drain side [13].…”

Section: Introductionmentioning

confidence: 99%