2021
DOI: 10.1109/tns.2021.3099202
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Impact of the Bitcell Topology on the Multiple-Cell Upsets Observed in VLSI Nanoscale SRAMs

Abstract: This paper presents an analysis of the multiple events (and more specifically, Multiple Cell Upsets or MCUs) that may occur at successive generations of bulk CMOS SRAMs operating under harsh conditions, such as in avionics or space. Such MCU distribution is greatly impacted by the bitcell topology, which, in the International Technology Roadmap for Semiconductors (ITRS) / International Roadmap for Devices and Systems (IRDS) history, experienced a drastic change in the transition between the 90-nm and the 65-nm… Show more

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Cited by 8 publications
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