Impact of the Different Parasitic Inductances on the Switching Behavior of SiC MOSFETs

Engelmann, Georges; Fritz, Niklas; Lüdecke, Christoph; Doncker, Rik W. De; Xu, Zhuxian; Lu, Xi; Chen, Chingchi; Kikuchi, Jun

doi:10.1109/epepemc.2018.8521911

Cited by 13 publications

(6 citation statements)

References 37 publications

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“…This observed increment in switching losses can be directly attributed to the presence of additional common source inductance, denoted as L S−c . Furthermore, it is noteworthy that the extent of switching losses is anticipated to further increase with an increase in the value of L S−c , as reported in literature [42]. These findings underscore the importance of careful consideration and optimization of the common source inductance in the design of the standard cell.…”

Section: The Gate Loop Inductancesupporting

confidence: 64%

Substrate Embedded Power Electronics Packaging for Silicon Carbide mosfets

Janabi,

Shillaber,

Ying

et al. 2024

IEEE Trans. Power Electron.

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This paper proposes a new power electronic packaging for discrete dies, namely Standard Cell which consists of a step-etched active metal brazed (AMB) substrate and a flexible printed circuit board (flex-PCB). The standard cell exhibits high thermal conductivity, complete electrical insulation, and low stray inductance, thereby enhancing the performance of SiC MOSFET devices. The standard cell has a stray power loop inductance of less than 1 nH and a gate loop inductance of less than 1.5 nH.The standard cell has a flat body with surface-mounting electrical connections on one side and direct thermal connections on the other. The use of flex-PCB die interconnection enables maximum utilization of source pads while providing a flexible gate-source connection and the converter PCB. This paper presents the design concept of the standard cell and experimentally validates its effectiveness in a converter system.

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Section: The Gate Loop Inductancesupporting

confidence: 64%

Substrate Embedded Power Electronics Packaging for Silicon Carbide mosfets

Janabi,

Shillaber,

Ying

et al. 2024

IEEE Trans. Power Electron.

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“…However, changing the inductance is not easy to do. The influence of inductance and its placement variation has been examined in [14]. It was concluded that the severity of oscillation during switching had been due to the lower ratio of device capacitance over inductance.…”

Section: Literature Review and Problem Statementmentioning

confidence: 99%

Capacitor for the voltage-surge suppression in a SiC-MOSFET half-bridge inverter

Hasanah,

Djuriatno,

Ardhenta

et al. 2023

EEJET

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This paper explores some efforts to suppress the voltage surge appearing during the operation of a SiC-MOSFET-based half-bridge circuit in an inverter topology. The study is important to carry out, as the voltage surge problem does not come up when a Si-IGBT is used as the switching component in the half-bridge; however, some applications demand certain properties like what is found in a SiC MOSFET. Compared to Si-IGBT with rise-time/fall-time larger than 100 ns in general, the use of SiC MOSFET is preferable due to its much shorter switching time, less than 50 ns, which brings about a much lower switching loss and lower operating temperature. However, the choice of the usual electrolytic capacitor in the dc-link would produce an undesired voltage surge during the half-bridge operation. The origin of the surge is sometimes assigned to the inductance parasitic effect of the SiC-MOSFET high frequency. This research proves the benefit of a film capacitor to suppress the surge due to its lower equivalent series resistance (ESR) than that of the electrolytic capacitor. The results contribute to the consideration to take during the circuit realization in various applications, as there are not many papers yet found discussing the use of film capacitor in the dc-link of a SiC-MOSFET half-bridge inverter. This study also reveals the importance of the film capacitor placement during the design stage of SiC-MOSFET applications; moreover, motor controllers being equipped with an inverter such as described in this study have not been found yet in the market. The efforts investigated in this work would help to control the undesirable voltage spikes that frequently occur when applying a SiC-MOSFET to a half-bridge inverter design

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“…Transistor switching power losses can be determined based on waveforms of the transistor drain-source voltage and the drain current collected during a double-pulse test. The doublepulse test is a well-known and widely acknowledged method of determining switching power losses in transistors [27][28][29][30]. A simplified schematic of the double-pulse test testbench has been shown in Fig.…”

Section: Power Losses In Mosfet Transistorsmentioning

confidence: 99%

“…A sophisticated design minimizing parasitic inductances in a power loop is required. Without minimizing parasitic inductances in the power loop, the switching speed of the transistors in the circuit may be limited [22,30]. It is also associated with overvoltages that appear between drain and source of the MOSFET switch, caused by parasitic inductances in the power loop and fast switching processes.…”

Section: Double-pulse Test Testbench For Sic Mosfet Power Modulesmentioning

confidence: 99%

“…Parasitic inductance in the power loop also affects the resulting switching energies obtained in the double-pulse test. It will positively affect the turn-on process -lowering turn-on switching energy, but at the same time, turn-off switching energy can rise to very high levels, increasing and dominating the sum of turnon and turn-off energies [30,34].…”

Section: Double-pulse Test Testbench For Sic Mosfet Power Modulesmentioning

confidence: 99%

See 1 more Smart Citation

Bulletin of the Polish Academy of Sciences: Technical Sciences

Zięba,

Rąbkowski

2022

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High-speed switching capabilities of SiC MOSFET power modules allow building high power converters working with elevated switching frequencies offering high efficiencies and high power densities. As the switching processes get increasingly rapid, the parasitic capacitances and inductances appearing in SiC MOSFET power modules affect switching transients more and more significantly. Even relatively small parasitic capacitances can cause a significant capacitive current flow through the SiC MOSFET power module. As the capacitive current component in the drain current during the turn-off process is significant, a commonly used method of determining the switching power losses based on the product of instantaneous values of drain-source voltage and drain current may lead to a severe error. Another problem is that charged parasitic capacitances discharge through the MOSFET resistive channel during the turn-on process. As this happens in the internal structure, that current is not visible on the MOSFET terminals. Fast switching processes are challenging to measure accurately due to the imperfections of measurement probes, like their output signals delay mismatch. This paper describes various problems connected with the correct determination of switching power losses in high-speed SiC MOSFET power modules and proposes solutions to these problems. A method of achieving a correct time alignment of waveforms collected by voltage and current probes has been shown and verified experimentally. In order to estimate SiC MOSFET channel current during the fast turn-off process, a method based on the estimation of nonlinear parasitic capacitances current has also been proposed and verified experimentally.

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Impact of the Different Parasitic Inductances on the Switching Behavior of SiC MOSFETs

Cited by 13 publications

References 37 publications

Substrate Embedded Power Electronics Packaging for Silicon Carbide mosfets

Substrate Embedded Power Electronics Packaging for Silicon Carbide mosfets

Capacitor for the voltage-surge suppression in a SiC-MOSFET half-bridge inverter

Bulletin of the Polish Academy of Sciences: Technical Sciences

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