Impact of the geometric parameters on the performance of silicon TG SOI N FinFET 5nm

Abstract

Semiconductor device dimensions have been downsized to nanoscale dimensions to upgrade the driving capacity and increasing speed. At the lower technology node, the performance of conventional CMOS circuits degrades because of the short channel effects (SCEs). the researchers expect to identify new solutions for different design issues as a result, the FinFET device has been introduced as an alternative to MOSFET for advanced scalability which allows the use of multi gates in order to dissipate lower power. This paper presents an analysis of TG N SOI (Semiconductor On insulator) FinFET 5 nm using Hafnium Dioxide and the Non-Equilibrium Green Function (NEGF) formalism to study the quantum effect. The different parameters such as leakage current, the ON current, the performance ratio ION/IOFF which are calculated and optimized. The aim and the novelty of this simulation is to present novel geometric parameters that improve the performance of the device, and hence to have optimized CMOS circuits.

A New GAA FinFET without n-well or p-well

“…Strain effect enhance band banding at the interface semiconductor-insulator and therefore enhances tunnelcurrent. The choice of the geometric parameters such as the gate oxide length can lead to the raising of the conduction band, and therefore, more potential in needed to create an inversion layer [5]-[10]- [22]. Table 4 displays performance parameters of both devices with 3 nm channel length.…”