Impact of the interfaces in the charge trap layer on the storage characteristics of ZrO2/Al2O3 nanolaminate-based charge trap flash memory cells

Holmium and titanium oxide nanolaminates by atomic layer deposition

“…HfO 2 -Al 2 O 3 [1], ZrO 2 -Al 2 O 3 [2][3][4][5][6], ZrO 2 -Y 2 O 3 [7], ZrO 2 -SiO 2 [7], HfO 2 -Al 2 O 3 [8,9], TiO 2 - [18,20], ZrO 2 -Er 2 O 3 [21], ZrO 2 -Gd 2 O 3 [22], and TiO 2 -Cr 2 O 3 [23].…”

“…Such oxide-based nanolaminates have been studied as materials able to provide good compromise between leakage current density and dielectric permittivity, enhancing charge storage capability of capacitor dielectrics while aiming at the improvement of the performance of, e.g., electroluminescent devices [10,14], field effect transistors [2,7,13,18,20], and memories [5,9,16,21,22]. Especially important industrially are the ZrO 2 -Al 2 O 3 -ZrO 2 structures [24] used in dynamic random access memory cells.…”

“…Nanolaminates of single oxides may be grown using different physical and chemical techniques, such as electron beam evaporation [13], sputtering [4], pulsed laser deposition [6] or, as apparently the most controlled method, atomic layer deposition (ALD) [1][2][3]5,7,[9][10][11][12][14][15][16][17][18][22][23][24]26]. Studies on ALD-grown nanolaminates containing rare earth oxides have so far been quite scarce [21,22], though, and none has been grown using Ti and Ho oxides as constituents.…”

The effect of the thickness of tunneling layer on the memory properties of (Cu2O)0.5(Al2O3)0.5 high-k composite charge-trapping memory devices

“…[25][26][27][28][29][30] Some definite experimental evidences identified that the charge-trapping behaviors in these multilayered memory devices should be ascribed to the inter-diffusion at the interface of different high-k oxides.…”

Improved Memory Characteristics by NH3Post Annealing for ZrO2Based Charge Trapping Nonvolatile Memory

“…However, using Si 3 N 4 charge trapping layer in a SONOS structure leads to poor retention, due to the shallow traps, and the small conduction band offset at the Si 3 N 4 /tunneling layer interface [3]. Employing high-k dielectrics as the charge trapping layer to improve memory characteristics in SONOS structure has been reported by many researchers [4][5][6][7][8][9]. The high-k charge trapping layer allows a higher electric field cross the tunneling layer, due to electric flux density continuity [3], and results in a modified Fowler-Nordheim tunneling, due to the smaller conduction band offset (CBO) with a Si substrate [10].…”