Impact of the Memory Hierarchy on Shared Memory Architectures in Multicore Programming Models

Badía, Rosa M.; Perez, Josep M.; Ayguadé, Eduard; Labarta, Jesús

doi:10.1109/pdp.2009.56

Cited by 4 publications

(3 citation statements)

References 11 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…In this case, the input, output, inout clauses are used to calculate the task data dependencies in order to build the task DAG. However, this does not mean that accessing data locally in NUMA systems is not important, as is shown by Badia et al (2009) for the SMPSs case when used in an SGI Altix.…”

Section: Smpss Runtime Specificsmentioning

confidence: 99%

Hierarchical Task-Based Programming With StarSs

Planas

Badía

Ayguadé

et al. 2009

The International Journal of High Performance Computing Applica

Self Cite

150

111

View full text Add to dashboard Cite

Programming models for multicore and many-core systems are listed as one of the main challenges in the near future for computing research. These programming models should be able to exploit the underlying platform, but also should have good programmability to enable programmer productivity. With respect to the heterogeneity and hierarchy of the underlying platforms, the programming models should take them into account but they should also enable the programmer to be unaware of the complexity of the hardware. In this paper we present an extension of the StarSs syntax to support task hierarchy. A motivation for such a hierarchical approach is presented through experimentation with CellSs. A prototype implementation of such a hierarchical task-based programming model that combines a first task level with SMPSs and a second task level with CellSs is presented. The preliminary results obtained when executing a matrix multiplication and a Cholesky factorization show the viability and potential of the approach and the current issues raised.

show abstract

Section: Smpss Runtime Specificsmentioning

confidence: 99%

Hierarchical Task-Based Programming With StarSs

Planas

Badía

Ayguadé

et al. 2009

The International Journal of High Performance Computing Applica

Self Cite

150

111

View full text Add to dashboard Cite

show abstract

“…Subsets of cores in a multicore machine may share different layers of memory levels. For example, usually, a small subset of cores shares L2 caches, while another subset of higher cardinality may share L3 caches, being the global memory shared by all the cores of the machine [33,34,35,36]. The modeling of such memory hierarchy sharing is still a challenge [1].…”

Section: Multicore Architectures -Models For Distributed and Shared M...mentioning

confidence: 99%

Memory aware load balance strategy on a parallel branch‐and‐bound application

Silva

Boeres

Drummond

et al. 2014

Concurrency and Computation

View full text Add to dashboard Cite

SUMMARYThe latest trends in high-performance computing systems show an increasing demand on the use of a large scale multicore systems in a efficient way, so that high compute-intensive applications can be executed reasonably well. However, the exploitation of the degree of parallelism available at each multicore component can be limited by the poor utilization of the memory hierarchy available. Actually, the multicore architecture introduces some distinct features that are already observed in shared memory and distributed environments. One example is that subsets of cores can share different subsets of memory. In order to achieve high performance it is imperative that a careful allocation scheme of an application is carried out on the available cores, based on a scheduling model that considers the main performance bottlenecks, as for example, memory contention. In this paper, the Multicore Cluster Model (MCM) is proposed, which captures the most relevant performance characteristics in multicores systems such as the influence of memory hierarchy and contention. Better performance was achieved when a load balance strategy for a Branch-and-Bound application applied to the Partitioning Sets Problem is based on MCM, showing its efficiency and applicability to modern systems.

show abstract

“…[2]. The applications have been written in StarSs [3], a task-level data-flow programming model similar to Cilk [4], RapidMind [5], Sequoia [6], and Tflux-DDM [7]. These programming models let the programmer write a seemingly sequential program, and annotate the input and output parameters of functions that can potentially execute as parallel tasks.…”

Section: Introductionmentioning

confidence: 99%

Interleaving granularity on high bandwidth memory architecture for CMPs

Cabarcas

Rico

Etsion

et al. 2010

2010 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation

View full text Add to dashboard Cite

Abstract-Memory bandwidth has always been a critical factor for the performance of many data intensive applications. The increasing processor performance, and the advert of single chip multiprocessors have increased the memory bandwidth demands beyond what a single commodity memory device can provide. The immediate solution is to use more than one memory device, and interleave data across them so they can be used in parallel as if they were a single device of higher bandwidth.In this paper we showed that fine-grain memory interleaving on the evaluated many-core architectures with many DRAM channels was critical to achieve high memory bandwidth efficiency. Our results showed that performance can degrade up to 50% due to achievable bandwidths being far from the maximum installed.

show abstract

Impact of the Memory Hierarchy on Shared Memory Architectures in Multicore Programming Models

Cited by 4 publications

References 11 publications

Hierarchical Task-Based Programming With StarSs

Hierarchical Task-Based Programming With StarSs

Memory aware load balance strategy on a parallel branch‐and‐bound application

Interleaving granularity on high bandwidth memory architecture for CMPs

Contact Info

Product

Resources

About