Impact of the Self-Heating Effect on Nanosheet Field Effect Transistor Performance

Smaani, Billel; Paras, Neha; Rahi, Shri Balmukund; Song, Young Suh; Yadav, Ramakant; Tayal, Shubham

doi:10.1149/2162-8777/acb96b

Cited by 11 publications

(4 citation statements)

References 34 publications

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“…It determines the gain and linearity of amplifiers, ensuring faithful signal reproduction and efficient power transfer in communication systems. 35,36 As shown in Figs. 4a-4c the g m improves as increasing the L g and reducing the T NS and W NS , respectively due to lower leakage current and enhanced driving characteristics of the device.…”

Section: Resultsmentioning

confidence: 82%

Optimizing Device Dimensions for Dual Material Junctionless Tree-FET: A Path to Improved Analog/RF Performance

Beebireddy,

Fatima,

2024

ECS J. Solid State Sci. Technol.

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This comprehensive study delves into the intricate analysis of the electrical and analog/RF performance of the Dual Material (DM) junctionless (JL) Tree-FET. During the optimization process, various DC and analog/RF metrics were taken into account. It is observed that, as the gate length decreases (12 nm to 8 nm), there is an increment in drain induced barrier lowering (DIBL), switching ratio (Ion/Ioff), and subthreshold swing (SS). Conversely, reducing the size of TNS (and WNS) from 10 nm to 5 nm (and 20 nm to 10 nm, respectively) lead to notable improvements, with a 34.4% (21.01%) decrease in SS, 93.19% (58.86%) decrease in DIBL, and 98.6% (41.06%) increase in Ion/Ioff. Furthermore, the analog/RF performance metrics of the device is carefully examined across dimensional variations, revealing significant improvements at the optimal values. Additionally, the study extends to the evaluation of inverter circuit characteristics with DM JL Tree-FET. Remarkably, the static noise margin (SNM) and delay exhibit 337.3 mV and 3.053 ps, respectively, positioning the device as a prime candidate for applications demanding low power consumption and high-frequency operation in future technology nodes.

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Section: Resultsmentioning

confidence: 82%

Optimizing Device Dimensions for Dual Material Junctionless Tree-FET: A Path to Improved Analog/RF Performance

Beebireddy,

Fatima,

2024

ECS J. Solid State Sci. Technol.

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“…Gate-all-around (GAA) devices, such as stacked nanowire field-effect transistors (SNW-FET) and stacked nanosheet FETs (SNS-FET), are the promising candidates for sub-7 nm technology [1,2]. GAA devices feature improved electrostatic integrity compared to FinFETs and demonstrate superior resilience to short-channel effects (SCEs) [3,4].…”

Section: Introductionmentioning

confidence: 99%

Investigation of spacer-engineered stacked nanosheet tunnel FET with varying design attributes

Jain,

Sawhney,

Kumar

2024

Phys. Scr.

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The stacked nanosheet field-effect transistors (SNS-FETs) are potential contenders for sub-7 nm technology. Device miniaturization leads to a larger off-state current and a higher subthreshold slope in SNS-FETs. Unlike SNS-FETs, the stacked nanosheet tunnelling field effect transistors (SNS-TFETs) function as switches in integrated circuits, featuring high performance and low power consumption. The endeavour aims to investigate how each design parameter optimises the switching characteristics of the SNS-TFET device. This paper examines various design attributes, such as different dielectric spacer materials, nanosheet width (NW), nanosheet thickness (NT), source doping, drain doping, etc. The Cogenda Visual TCAD serves as a tool for conducting device simulations. According to the simulation study, the use of a high-k hafnium dioxide (HfO2) spacer produces a higher switching ratio ( ) and a lower subthreshold swing (20.303 mV/decade). Using either low-k or no spacers reduces the overall gate capacitance and unit frequency gain compared to high-k spacers. Upscaling the nanosheet width (10 to 50 nm) enhances the switching ratio by and transconductance by 61.92%. Downscaling the nanosheet thickness (6 to 4 nm) at the optimized nanosheet width (50 nm) improves the switching ratio by 1.88. Increasing the gate length from 8 to 16 nm reduces the leakage current by A and improves the switching ratio by . An increase in the source doping level from to cm-3 results in a decrease in the switching ratio and a 2.48-fold increase in the subthreshold swing. Furthermore, the findings indicate that drain doping is crucial in determining ambipolar current. In SNS-TFET, ambipolar current reduces significantly when drain doping is cm-3. Thus, the proposed work addresses the limitations of scaling and optimised design parameter characteristics for low-power nanoscale circuits.

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“…As the feature size of advanced MOSFETs scales down, many new materials, new process technologies, and new transistor architectures have been introduced in very large-scale integrated circuits (VLSIs). [1][2][3][4][5][6][7] However, as the technology node scales down to 3 nm node and beyond, the fin field effective transistor (FinFET) faces several challenges such as the process fragility of ultra-steep and high fins, degradation of carrier mobility, and unavoidable shortchannel-effects (SCEs), which greatly limit its continuous application for future advanced integrated circuits (ICs). [8][9][10][11] In order to fulfill the demand for the higher effective width (W eff )/footprint ratios and better gate controllability to suppress the SCEs, vertically stacked horizontal gate-all-around (GAA) Si nanosheet field-effecttransistors (NSFETs) have been considered as one of the most promising candidates at 3 nm node and beyond.…”

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confidence: 99%

Stacked Si Nanosheets Gate-All-Around Transistors with Silicon-on-Nothing Structure for Suppressing Parasitic Effects and Improving Circuits’ Performance

Li,

Cao,

Zhang

et al. 2024

ECS J. Solid State Sci. Technol.

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We propose a novel silicon-on-nothing (SON) structure with an air sub-fin for suppressing the parasitic channel effects on stacked Si nanosheets (NS) gate-all-around (GAA) transistors and a systematic investigation is carried out by 3D TCAD simulation. The SON structure could be fabricated using a backside selective etching technique. The proposed SON NSFETs with a designed air sub-fin structure demonstrates systematic advantages, including 40% off-state current reduction in the sub-channel, and 51.37% promotion for on-off current ratio (ION/IOFF) and 7.04% reduction in effective capacitance. Moreover, there is approximately 21.62% power reduction under the same frequency, and about 16.30% energy reduction under the same delay in 17-stage ring oscillators (ROs). The SON NSFETs-based 6T-SRAM exhibits decreased read time and write time by 14.66% and 67.53%, respectively, compared with those of the conventional GAA NSFETs-based 6T-SRAM.

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Impact of the Self-Heating Effect on Nanosheet Field Effect Transistor Performance

Cited by 11 publications

References 34 publications

Optimizing Device Dimensions for Dual Material Junctionless Tree-FET: A Path to Improved Analog/RF Performance

Optimizing Device Dimensions for Dual Material Junctionless Tree-FET: A Path to Improved Analog/RF Performance

Investigation of spacer-engineered stacked nanosheet tunnel FET with varying design attributes

Stacked Si Nanosheets Gate-All-Around Transistors with Silicon-on-Nothing Structure for Suppressing Parasitic Effects and Improving Circuits’ Performance

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