Impact of Various Polysilicon Deposition Process on Thin Gate-Oxide Properties in Submicron CMOS Technology

Abstract

The dielectric quality (defect density, Do and breakdown strength, Fbd) of 150Å SiO2 gate oxide (GOX) films grown by conventional or stacked oxidation scheme are discussed from the leakage measurements of polysilicon capacitors on test structure simulating our submicron CMOS process. Various polysilicon (poly) deposition processes from silane pyrolysis (570°C -620°C) were used by the low pressure chemical vapor deposition (LPCVD) technique. Both in situ and ex situ poly doping by phosphorus (P) were used to ascertain their impact on the GOX properties. The substructural characteristics of the poly/SiO2 and SiO2/Si interfaces generated by various combinations of GOX and poly deposition processes were done by the high resolution TEM lattice fringe technique under phase contrast mode.

Surface topography of phosphorus doped polysilicon

“…11 The poly-Si deposition and doping processes establish the microstructure, dopant concentrations, and surface topography of these films. [2][3][4][13][14][15][16][17][18] The purpose of this work was to evaluate the surface topography of poly-Si films that are used for double-poly-Si capacitor applications. [2][3][4][13][14][15][16][17][18] The purpose of this work was to evaluate the surface topography of poly-Si films that are used for double-poly-Si capacitor applications.…”

“…12 These properties, in turn, affect gate oxide and interpoly oxide quality. We have deposited poly-Si films that were subsequently doped using either PH 3 or POCl 3 gas-phase diffusion as well as films that were in situ doped. We have deposited poly-Si films that were subsequently doped using either PH 3 or POCl 3 gas-phase diffusion as well as films that were in situ doped.…”