Impacts of Clock Frequency and Sampling Intervals on Power Side-Channel Leakage of AES Circuits

Miura, Yuto; Nishikawa, Hiroki; Kong, Xiangbo; Tomiyama, Hiroyuki

doi:10.1109/iceic61013.2024.10457150

2024 International Conference on Electronics, Information, and Communication (ICEIC) 2024

DOI: 10.1109/iceic61013.2024.10457150

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Impacts of Clock Frequency and Sampling Intervals on Power Side-Channel Leakage of AES Circuits

Yuto Miura,

Hiroki Nishikawa,

Xiangbo Kong

et al.

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Impacts of Clock Frequency and Sampling Intervals on Power Side-Channel Leakage of AES Circuits

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