2014 IEEE International Reliability Physics Symposium 2014
DOI: 10.1109/irps.2014.6860634
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Impacts of Cu contamination in 3D integration process on memory retention characteristics in thinned DRAM chip

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Cited by 8 publications
(2 citation statements)
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“…Lee et al examined copper contamination of the backside grinding process used in thin MOS-FET device fabrication. They made evaluated by MOS capacitance generation-recombination lifetime measurements and found that the copper impurities in-diffuse into the device active region during the backside grinding process and CMP process [9,56,57,58]. Copper impurities then form deep-energy level defects in the silicon band-gap.…”
Section: Gettering Technology Design For Back-side-illuminated Cmomentioning
confidence: 99%
“…Lee et al examined copper contamination of the backside grinding process used in thin MOS-FET device fabrication. They made evaluated by MOS capacitance generation-recombination lifetime measurements and found that the copper impurities in-diffuse into the device active region during the backside grinding process and CMP process [9,56,57,58]. Copper impurities then form deep-energy level defects in the silicon band-gap.…”
Section: Gettering Technology Design For Back-side-illuminated Cmomentioning
confidence: 99%
“…In addition, during the fabrication of BSI-based 3D stacked CMOS image sensors, the device Si wafer must be thinned by mechanical grinding and chemical mechanical polishing (CMP). The thin-wafer fabrication process has a risk of degradation of the electrical performance of the CMOS image sensor owing to easy metallic impurity contamination into the active region of the photodiode [ 6 , 7 , 8 ]. Therefore, the fabrication process of 3D-stacked BSI image sensors has many chances for metallic impurities to be introduced compared with that of conventional front-side illuminated (FSI) image sensors.…”
Section: Introductionmentioning
confidence: 99%