Impacts of the pads, ESD diodes and package parasitic on the noise figure and gain of a common source low noise amplifier

Salmeh, Roghoyeh

doi:10.1109/mwscas.2010.5548788

Cited by 4 publications

(2 citation statements)

References 10 publications

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“…Therefore, on-chip ESD protection is important for both component-level and system-level ESD protection. In high-speed applications, the ESD protection device may affect circuit performance via its parasitic capacitance at the I/O pad [ 6 , 7 ]. Thus, reducing the parasitic capacitance is one of the most important considerations for high-speed applications [ 8 , 9 ].…”

Section: Introductionmentioning

confidence: 99%

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π-Shape ESD Protection Design for Multi-Gbps High-Speed Circuits in CMOS Technology

2023

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CMOS integrated circuits are vulnerable to electrostatic discharge (ESD); therefore, ESD protection circuits are needed. On-chip ESD protection is important for both component-level and system-level ESD protection. In this work, on-chip ESD protection circuits for multi-Gbps high-speed applications are studied. π-shaped ESD protection circuit structures realized by staked diodes with an embedded silicon-controlled rectifier (SCR) and resistor-triggered SCR are proposed. These test circuits are fabricated in CMOS technology, and the proposed designs have been proven to have better ESD robustness and performance in high-speed applications.

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Section: Introductionmentioning

confidence: 99%

“…Therefore, to cancel the parasitic capacitance of ESD applications, the inductor is usually added to the ESD protection circuit. For example, the T-coil-based ESD protection circuit for 5 GHz LNAs has been presented [ 7 ]. This design has achieved 2 kV human body model (HBM) ESD robustness with 2 dB degradation.…”

Section: Introductionmentioning

confidence: 99%