Impacts of though-DRAM vias in 3D processor-DRAM integrated systems

Wu, Qi; Rose, K.; Lu, Jian‐Qiang; Zhang, Tong

doi:10.1109/3dic.2009.5306577

Cited by 15 publications

(7 citation statements)

References 12 publications

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“…In addition, other TSVs are required for control, power distribution and thermal dissipation. On the assumption that the power supply voltage is 1V, a practical aspect ratio for TSVs is between 10:1 to 5:1, in which signal TSVs are dominant ones [15] [16]. In our paper, a pillar is defined as a bunch of TSVs, including TSVs for data, control and power distribution.…”

Section: Analysis Of the Tsvmentioning

confidence: 99%

A study of Through Silicon Via impact to 3D Network-on-Chip design

Liljeberg

Tenhunen

2010

2010 International Conference on Electronics and Information Engineering

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The adoption of a 3D Network-on-Chip (NoC) design depends on the performance and manufacturing cost of the chip. Therefore, a study of Through Silicon Via (TSV), that connects different layers of a 3D chip, is crucial. In this paper, we analysis the impact of TSV design in 3D NoCs. A 3D NoC with five layers is modeled based on modern 2D chips. We discuss the TSV number required for a 3D NoC. Different placements of half and quarter layer-layer connections are explored. We present benchmark results using a cycle accurate full system simulator based on realistic workloads. Experiments show that under different workloads, the average network latencies in full and half layer-layer connection are reduced by 5.24% and 2.18% respectively, compared with quarter design. Our analysis and experiment results provide a guideline for designing TSVs in 3D NoCs to leverage the tradeoff between performance and manufacturing cost.

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Section: Analysis Of the Tsvmentioning

confidence: 99%

A study of Through Silicon Via impact to 3D Network-on-Chip design

Liljeberg

Tenhunen

2010

2010 International Conference on Electronics and Information Engineering

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“…In our paper, a pillar is defined as a bunch of TSVs, including TSVs for data, control and power distribution. On the assumption that the power supply voltage is 1V, a practical aspect ratio for TSVs is between 10:1 to 5:1, in which signal TSVs are dominant ones [13] [14].…”

Section: B Through Silicon Viamentioning

confidence: 99%

Optimal number and placement of Through Silicon Vias in 3D Network-on-Chip

Liljeberg

Tenhunen

2011

14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems

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In this paper, we analyze the performance impact of different number of Through Silicon Vias (TSVs) in 3D Networkon-Chip (NoC). The adoption of a 3D NoC design depends on the performance and manufacturing cost of the chip. Therefore, a study of the placement of the TSV, that connects different layers of a 3D chip, is crucial. A 64-core 3D NoC is modeled based on state-of-the-art 2D chips. We discuss the number of TSVs required for a 3D NoC. Different placements of layerlayer connections are explored. We present benchmark results using a cycle accurate full system simulator based on realistic workloads. Experiments show that under different workloads, the average network latencies in two configurations (full and quarter connection) are reduced by 14.78% and 7.38% respectively, compared with the one-eighth connection design. The improvement of performance is a trade-off of manufacturing cost. Our analysis and experiment results provide a guideline for selecting optimal number of TSVs in 3D NoCs.

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“…Thus, more memory can be accommodated without scaling down the geometries. Therefore, multicore processor dies and multicore memory dies stacking has been considered as a solution to enable ultra-high-performance applications [Loh 2008;Saito et al 2009;Jacob et al 2009;Wu et al 2009;Healy et al 2010].…”

Section: Introductionmentioning

confidence: 99%

Yield-enhancement schemes for multicore processor and memory stacked 3D ICs

Huang

2014

ACM Trans. Embed. Comput. Syst.

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A three-dimensional (3D) integrated circuit (IC) with multiple dies vertically connected by through-siliconvia (TSV) offers many benefits over current 2D ICs. Multicore logic-memory die stacking has been considered as one candidate for 3D ICs by utilizing the TSV to provide high data bandwidth between logic and memory. However, 3D ICs suffer from the low-yield issue. This article proposes effective yield-enhancement techniques for multicore die-stacked 3D ICs. Two reconfiguration schemes are proposed to logically swap the positions of cores in the dies of 3D ICs such that the yield of 3D ICs is increased. Two algorithms also are proposed to determine the reconfiguration effectively. Simulation results show that the proposed reconfiguration schemes can achieve a yield gain ranging from 1% to 11%.

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Impacts of though-DRAM vias in 3D processor-DRAM integrated systems

Cited by 15 publications

References 12 publications

A study of Through Silicon Via impact to 3D Network-on-Chip design

A study of Through Silicon Via impact to 3D Network-on-Chip design

Optimal number and placement of Through Silicon Vias in 3D Network-on-Chip

Yield-enhancement schemes for multicore processor and memory stacked 3D ICs

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