2018
DOI: 10.1109/ted.2018.2801361
|View full text |Cite
|
Sign up to set email alerts
|

Impacts of Trap-State Generation on Tunnel Thin-Film Transistor

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
1

Citation Types

0
1
0

Year Published

2019
2019
2023
2023

Publication Types

Select...
6

Relationship

1
5

Authors

Journals

citations
Cited by 6 publications
(1 citation statement)
references
References 34 publications
0
1
0
Order By: Relevance
“…It indicates the endurance operation would damage the channel film and gate-dielectric/poly-Si channel interface, resulting in the generation of trap state density. The positive and negative gate bias stress effect of poly-Si tunnel TFT may generate the trap state density and lead to the degraded electrical characteristics, [32][33][34] which is known as the dynamic stress effect. Therefore, the increased V TH of poly-Si FeT-TFT within 500 endurance cycles can be attributed to the dynamic stress issue due to the maintained MW, while the reduced MW from 500 to 10 4 endurance cycles is attributed to the weakened polarization switching of the ferroelectric layer.…”
Section: Resultsmentioning
confidence: 99%
“…It indicates the endurance operation would damage the channel film and gate-dielectric/poly-Si channel interface, resulting in the generation of trap state density. The positive and negative gate bias stress effect of poly-Si tunnel TFT may generate the trap state density and lead to the degraded electrical characteristics, [32][33][34] which is known as the dynamic stress effect. Therefore, the increased V TH of poly-Si FeT-TFT within 500 endurance cycles can be attributed to the dynamic stress issue due to the maintained MW, while the reduced MW from 500 to 10 4 endurance cycles is attributed to the weakened polarization switching of the ferroelectric layer.…”
Section: Resultsmentioning
confidence: 99%