1989
DOI: 10.1109/55.32439
|View full text |Cite
|
Sign up to set email alerts
|

Implanted silicon JFET on completely depleted high-resistivity devices

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
2
1
1

Citation Types

0
28
0

Year Published

1990
1990
2020
2020

Publication Types

Select...
4
4

Relationship

1
7

Authors

Journals

citations
Cited by 110 publications
(28 citation statements)
references
References 7 publications
0
28
0
Order By: Relevance
“…In particular, the minimization in the number of hightemperature thermal cycles during fabrication has been stressed. As a result the processing used for the circuitry in the previous work is somewhat restricted in comparison to modem integrated-circuit processes [1][2][3][4]. In contrast, we have developed a detector process that overcomes the hightemperature processing limitations and allows the use of standard MOS technology to realize the readout circuitry [5][6].…”
Section: Process Design Considerationsmentioning
confidence: 99%
See 2 more Smart Citations
“…In particular, the minimization in the number of hightemperature thermal cycles during fabrication has been stressed. As a result the processing used for the circuitry in the previous work is somewhat restricted in comparison to modem integrated-circuit processes [1][2][3][4]. In contrast, we have developed a detector process that overcomes the hightemperature processing limitations and allows the use of standard MOS technology to realize the readout circuitry [5][6].…”
Section: Process Design Considerationsmentioning
confidence: 99%
“…In previously published work much emphasis has been placed on the special processing techniques necessary to develop detectors with low reverse-bias leakage currents [1][2][3][4]. In particular, the minimization in the number of hightemperature thermal cycles during fabrication has been stressed.…”
Section: Process Design Considerationsmentioning
confidence: 99%
See 1 more Smart Citation
“…The starting material is a 300-m-thick-high resistivity (2 k cm) silicon substrate. Each SDD of the array has the input JFET of the readout electronics directly integrated in close proximity of the collecting anode to reach optimum performance [8]. The hole in the center of the array has been laser cut.…”
Section: Spectrometer Architecturementioning
confidence: 99%
“…This results in a reduction in the electronic noise, since the parasitic capacitance associated with preamplifier-detector connection is minimised. Furthermore, it reduces the need for shielding against capacitively-coupled pickup noise [1] and simplifies the circuit process assembly [2], [3]. However, these benefits must be traded off against the increased complexity (and potentially cost) of fabrication.…”
mentioning
confidence: 99%