Implement Embedded Controller Using FPGA Chip

Abstract

<p>The designer of an FPGA embedded processor system has complete flexibility to select any combination of peripherals and controllers. In fact, the designer can invent new, unique peripherals that can be connected directly to the processor bus. If a designer has a non-standard requirement for a peripheral set, this can be met easily with an FPGA embedded processor system. For example, a designer would not easily find an off-the-shelf processor with ten UARTs. However, in an FPGA, this configuration is very easily accomplished.</p>

Hardware-software partitioning using three-level hybrid algorithm for system-on-chip platform

“…The first step in GA is to initialise all the populations of solutions. The fitness or cost of each solution is evaluated using (1). Once the fitness evaluation is done, the solutions used to perform crossover and mutation will be selected through a selection process.…”

“…To demonstrate the PSO model, the population of solutions are first initialised, and the fitness for each solution is evaluated. The fitness function is the cost function as shown in (1). The velocity for each solution is initially set to zero.…”

“…In the second testing, the algorithms are iterated using values as tabulated in Table 1 for a 12-nodes application. In both testings, the cost is calculated using (1). The best cost is determined as the unchanging cost in 50 consecutive iterations.…”

“…Hardware refers to the FPGA that runs as parallel circuits, whereas software refers to the HPS that executes sequential instructions. FPGA tends to improve the execution time through its parallel processing capability but uses many resources [1], which lead to high power consumption. Hardware-software partitioning is proposed for the combination of FPGA and HPS in embedded system applications to require few resources and reduce the power consumption and execution time.…”

Embedded processor system for controllable period-width multichannel pulse width modulation signals

“…In the first step a processing unit, block RAM (BRAM) controller IP core, General purpose input/output (GPIO) IP core, and four timers IP cores (timer_0, timer_1, timer_2 and timer_3) are instantiated to the IP integrator diagram as shown in Figure 2. The processing unit in PS domain contains two processor cores, each of them includes 32KB instruction cache, 32 KB data cache, floating point unit and memory management unit (MMU) to provide access to the one mega byte dual data rate dynamic RAM (DDR3) available on the evaluation board [21,[26][27][28][29][30]. The block RAM is 64 KB two ports memory, it is mostly used as a boot memory.…”