Implementation and acceleration scheme of Heart sound classification Algorithm based on SOC-FPGA

Li, Guozheng; Yang, Hongbo; Guo, Tao; Wang, Weilain

doi:10.1145/3523286.3524551

Cited by 2 publications

(1 citation statement)

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“…A heart sound classification algorithm was implemented using CNN on a smallscale SoC-FPGA with fewer resources in [34]. FPGA with the parallelism of CNN and several techniques, such as loop unrolling, a fixed point of the model parameter, and reducing global memory, were applied to accelerate the algorithm.…”

Section: Literature Reviewmentioning

confidence: 99%

A Federated Learning Model Based on Hardware Acceleration for the Early Detection of Alzheimer’s Disease

Khalil,

Khan Mamun,

Sherif

et al. 2023

Sensors

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Alzheimer’s disease (AD) is a progressive illness with a slow start that lasts many years; the disease’s consequences are devastating to the patient and the patient’s family. If detected early, the disease’s impact and prognosis can be altered significantly. Blood biosamples are often employed in simple medical testing since they are cost-effective and easy to collect and analyze. This research provides a diagnostic model for Alzheimer’s disease based on federated learning (FL) and hardware acceleration using blood biosamples. We used blood biosample datasets provided by the ADNI website to compare and evaluate the performance of our models. FL has been used to train a shared model without sharing local devices’ raw data with a central server to preserve privacy. We developed a hardware acceleration approach for building our FL model so that we could speed up the training and testing procedures. The VHDL hardware description language and an Altera 10 GX FPGA are utilized to construct the hardware-accelerator approach. The results of the simulations reveal that the proposed methods achieve accuracy and sensitivity for early detection of 89% and 87%, respectively, while simultaneously requiring less time to train than other algorithms considered to be state-of-the-art. The proposed algorithms have a power consumption ranging from 35 to 39 mW, which qualifies them for use in limited devices. Furthermore, the result shows that the proposed method has a lower inference latency (61 ms) than the existing methods with fewer resources.

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Section: Literature Reviewmentioning

confidence: 99%