Implementation and Analysis of Methods for Error Detection and Correction on FPGA

Đug, Mehmed; Krstić, Miloš; Jokić, Dejan

doi:10.1016/j.ifacol.2018.07.178

Cited by 5 publications

(2 citation statements)

References 12 publications

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“…The researcher selected the boolean difference error calculus (BDEC) method that was previously suggested in the literature and expanded it in two ways: first, to account for the impact of reliability-enhancement strategies like redundancy, and second, to encompass sequential circuit parts [12]. Dug et al [13] constructed and examined two techniques for creating fault-tolerant pipelined sequential and combinational circuits on a FPGA board. Error-detection and partial error correction (EDPEC), and full-error detection and correction (FEDC) were considered as evaluated approaches.…”

Section: Previous Workmentioning

confidence: 99%

Design and analysis of fault-tolerant sequential logic circuits for safety-critical applications

Khairullah,

Qassabbashi,

Kareem

2024

Bulletin EEI

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Safety-critical systems used in applications that demand high levels of dependability, efficiency, and fault-tolerance often use sequential logic circuits in its design and implementation. The safety-critical digital system typically uses latches, flip-flops, and other memory elements, which are prone to the effects of natural faults and single event upsets (SEUs) caused by radiation-induced effects. The faults can lead to subsystem failures due to the continuous advancement in the realization of the small size transistor. To design a reliable digital-based system, it is essential to develop new fault-tolerance approaches that are integrated into the design of sequential logic circuits. This work proposes a novel fault-tolerant approach based on the redundancy of sequential logic circuit, which consists of a variety of design components, D flip-flop storage elements linked to a fault injection unit, a duplicate modular redundancy, and data monitoring units with a switching circuit. The experimental simulation results using a five-state Markov chain analysis model prove that the proposed fault-tolerant system can achieve 0.99999998 for reliability of the fault detection coverage (C) which equal to 0.99999. Finally, we believe that using this new approach of fault-tolerance and redundancy would improve the dependability and reliability of next generation safety-critical applications.

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Section: Previous Workmentioning

confidence: 99%

Design and analysis of fault-tolerant sequential logic circuits for safety-critical applications

Khairullah,

Qassabbashi,

Kareem

2024

Bulletin EEI

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“…The use of correction circuits requires the introduction of considerable redundancy determined by the need to compare the results of calculations from several circuits at once. For example, the widely known majority correction circuit [5][6][7][8][9][10][11], as well as its modifications [12][13][14], has three identical computing units. The correction of signals can be carried out at various levels of the control system architecture, including memory, arithmetic-logical components, etc.…”

Section: Introductionmentioning

confidence: 99%

Boolean-Complement Based Fault-Tolerant Electronic Device Architectures

Ефанов

Sapozhnikov

2021

Autom Remote Control

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We propose new fault-tolerant architectures, which, in contrast to the well-known double and triple modular redundancy architectures, include only one copy of the original circuit. In the new architectures, a signal error detection circuit is used to select the functions to be corrected. The circuit is built on the basis of the Boolean complement method with parity check of calculations. A generalized architecture with Boolean complement based signal correction is presented. This architecture permits one to design the simplest fault-tolerant circuits. Algorithms for designing signal error detection circuits, as well as examples of their application, are given.

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