Implementation and Comparison of Several Register Transfer Level Simulation Engines for the HDLRuby Language

Abstract

HDLRuby is a new hardware description language (HDL) based on Ruby that focuses on design productivity. This language is already mature enough to design complex circuits but it still requires a fast simulator to become a realistic alternative to de-facto standards like VHDL or Verilog HDL. In this paper, we present and compare four implementation strategies for simulating hardware descriptions in HDLRuby. The first strategy consists in generating Verilog HDL and using a state-of-the-art simulator for this language, the second one generates the C code of a standalone simulator, the third one directly executes the internal representation (IR) of HDLRuby using the Ruby interpreter, and the fourth one integrates compiled C with Ruby for fast interpretation of the HDLRuby IR. Experimental results show that the last approach is on average the fastest, and does not have any case of plummeting performance contrary to the other strategies.