Implementation and Design Space Exploration of a Turbo Decoder in High-Level Synthesis

Design Analysis of Turbo Decoder Based on One MAP Decoder Using High Level Synthesis Tool

“…The implemented designs were compared using HLS tools and RTL designs in [6] and they found that 40% of the cases studied proved that HLS tools equaled or outperformed RTL designs from In terms of performance and better use of resources, they also studied whether the size of the design affects performance quality, and they concluded that HLS tools are suitable for both large and small designs. In paper [7] high level synthesis tool was used for implementing turbo decoder algorithms with exploration of HLS optimization using different directives for designing several archi-tecture designs of turbo decoders. This work designs a normal turbo decoder with two decoders in iterative fashion in C++ language and make it fully parallel by unroll directive using Vivado HLS tool and make a comparative with a proposed turbo decoder with one decoder in iterative fashion and again made it fully parallels by same directive.…”

“…One of the things that has been achieved in communication systems is to increase reliability specially in wireless communications because it transfers on noisy channel. Forward Error Correction (FEC), have been put in place to get the correct information for the recipient to increase reliability [7]. Forward Error Correction (FEC), is amathematical method that adds some known values to the message sent by the sender and the receiver of this message can received it correctly even in case of errors in the message during the transfer.…”