Implementation and Evaluation of a Dynamically Routed Processor Operand Network

Gratz, Paul V.; Sankaralingam, Karthikeyan; Hanson, Heather; Shivakumar, Premkishore; McDonald, Robert; Keckler, Stephen W.; Burger, Doug

doi:10.1109/nocs.2007.23

Cited by 41 publications

(22 citation statements)

References 22 publications

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“…Simplifying to a 16-bit data path and scaling for technology, our model projects area of a µcore to be 0.028mm 2 . We conservatively assumed the interconnect's area is 10% of processor area, similar to reported results [13]. Based on this model, a single PLUG tile's area is 2.34 mm 2 .…”

Section: Early Estimates: Are Plugs Buildable?mentioning

confidence: 88%

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Design and implementation of the PLUG architecture for programmable and efficient network lookups

Kumar

Carli

Kim

et al. 2010

Proceedings of the 19th International Conference on Parallel Architectures and Compilation Techniques

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This paper proposes a new architecture called Pipelined LookUp Grid (PLUG) that can perform data structure lookups in network processing. PLUGs are programmable and through simplicity achieve power efficiency. We draw upon the insights that data structure lookups have natural structure that can be statically determined and exploited. The PLUG execution model transforms data-structure lookups into pipelined stages of computation and associates small code-blocks with data. The PLUG architecture is a tiled architecture with each tile consisting predominantly of SRAMs, a lightweight no-buffering router, and an array of lightweight computation cores. Using a principle of fixed delays in the execution model, the architecture is contention-free and completely statically scheduled thus achieving high energy efficiency. The architecture enables rapid deployment of new network protocols and generalizes as a data-structure accelerator.This paper describes the PLUG architecture, the compiler, and evaluates our RTL prototype PLUG chip synthesized on a 55nm technology library. We evaluate six diverse high-end network processing workloads including IPv4, IPv6, and Ethernet forwarding. We show that at a 55nm technology, a 16-tile PLUG occupies 58mm 2 , provides 4MB on-chip storage, and sustains a clock frequency of 1 GHz. This translates to 1 billion lookups per second, a latency of 18ns to 219ns, and average power less than 1 watt.

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Section: Early Estimates: Are Plugs Buildable?mentioning

confidence: 88%

“…Compared to conventional OCNs [13], this network requires no buffering or flow control as the OCN traffic is guaranteed to be conflict-free. The router's high level schematic is shown in Figure 4d.…”

Section: Microarchitecture: On-chip Networkmentioning

confidence: 99%

Design and implementation of the PLUG architecture for programmable and efficient network lookups

Kumar

Carli

Kim

et al. 2010

Proceedings of the 19th International Conference on Parallel Architectures and Compilation Techniques

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“…We also leverage look-ahead adaptive routing computation; the router calculates at most two alternative output ports for the next hop [20], [22], [30]. Advanced bundles [24], [31] encoding the packet destination traverse the link to the next hop while the flit is in the ST stage as shown in Fig. 8.…”

Section: Dbss Router Microarchitecturementioning

confidence: 99%

Holistic Routing Algorithm Design to Support Workload Consolidation in NoCs

Jerger

Wang

et al. 2014

IEEE Trans. Comput.

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Abstract-To provide efficient, high-performance routing algorithms, a holistic approach should be taken. The key aspects of routing algorithm design include adaptivity, path selection strategy, VC allocation, isolation and hardware implementation cost; these design aspects are not independent. The key contribution of this work lies in the design of a novel selection strategy, Destination-Based Selection Strategy (DBSS) which targets interference that can arise in many-core systems running consolidation workloads. In the process of this design, we holistically consider all aspects to ensure an efficient design. Existing routing algorithms largely overlook issues associated with workload consolidation. Locally adaptive algorithms do not consider enough status information to avoid network congestion. Globally adaptive routing algorithms attack this issue by utilizing network status beyond neighboring nodes. However, they may suffer from interference, coupling the behavior of otherwise independent applications. To address these issues, DBSS leverages both local and non-local network status to provide more effective adaptivity. More importantly, by integrating the destination into the selection procedure, DBSS mitigates interference and offers dynamic isolation among applications. Results show that DBSS offers better performance than the best baseline selection strategy and improves the energy-delay product for medium and high injection rates; it is well suited for workload consolidation.

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“…Operand Network: The Operand Network connects the TRIPS processor tiles and transmits operands between execution tiles, the register file tiles, and the data cache tiles [24]. The TRIPS compiler's instruction placer takes as input the tile topology and the dependencies between the instructions in each block.…”

Section: Feeds and Speedsmentioning

confidence: 99%

Tera-OP Reliable Intelligently Adaptive Processing System (TRIPS) Implementation

Keckler¹,

Burger²,

McKinley³

et al. 2008

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Implementation and Evaluation of a Dynamically Routed Processor Operand Network

Cited by 41 publications

References 22 publications

Design and implementation of the PLUG architecture for programmable and efficient network lookups

Design and implementation of the PLUG architecture for programmable and efficient network lookups

Holistic Routing Algorithm Design to Support Workload Consolidation in NoCs

Tera-OP Reliable Intelligently Adaptive Processing System (TRIPS) Implementation

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