Implementation and Performance Evaluation of Various Reversible Vedic Multiplier Architectures for Reversible Digital Filters

Swathi, U.; U, Smitha

doi:10.1007/978-981-16-2761-3_81

Cited by 1 publication

(3 citation statements)

References 16 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Design in [16] is considered the best in the literature regarding QC, CI, gate count and TRLIC. In contrast, the design provided in [5] is regarded as the best literature design in the GO.…”

Section: Resultsmentioning

confidence: 99%

“…Table 2 explores the reduction of the reversible design characteristics of the proposed design. The quantum cost is reduced to 94% of the design in [16], and a total TRLIC reduction to 90.3%. This reduction is because the design of 4-bit binary adders utilizes more gates and generates more garbage outputs than compressor adders.…”

Section: Resultsmentioning

confidence: 99%

“…However, it was implemented using the highest number of reversible gates and garbage outputs. Swathi et al [16] proposed six different reversible Vedic multiplier architectures for 2 × 2, 4 × 4, 8 × 8, and 16 × 16. They designed the multiplier N × N using the blocks of the M × M where M = N/2.…”

Section: Adder Compressorsmentioning

confidence: 99%

See 2 more Smart Citations

Optimization of Quantum Cost for Low Energy Reversible Signed/Unsigned Multiplier Using Urdhva-Tiryakbhyam Sutra

Elmenyawi¹,

Tawfeek²

2023

Computer Systems Science and Engineering

View full text Add to dashboard Cite

One of the elementary operations in computing systems is multiplication. Therefore, high-speed and low-power multipliers design is mandatory for efficient computing systems. In designing low-energy dissipation circuits, reversible logic is more efficient than irreversible logic circuits but at the cost of higher complexity. This paper introduces an efficient signed/unsigned 4 × 4 reversible Vedic multiplier with minimum quantum cost. The Vedic multiplier is considered fast as it generates all partial product and their sum in one step. This paper proposes two reversible Vedic multipliers with optimized quantum cost and garbage output. First, the unsigned Vedic multiplier is designed based on the Urdhava Tiryakbhyam (UT) Sutra. This multiplier consists of bitwise multiplication and adder compressors. Compared with Vedic multipliers in the literature, the proposed design has a quantum cost of 111 with a reduction of 94% compared to the previous design. It has a garbage output of 30 with optimization of the best-compared design. Second, the proposed unsigned multiplier is expanded to allow the multiplication of signed numbers as well as unsigned numbers. Two signed Vedic multipliers are presented with the aim of obtaining more optimization in performance parameters. DesignI has separate binary two's complement (B2C) and MUX circuits, while DesignII combines binary two's complement and MUX circuits in one circuit. DesignI shows the lowest quantum cost, 231, regarding state-ofthe-art. DesignII has a quantum cost of 199, reducing to 86.14% of DesignI. The functionality of the proposed multiplier is simulated and verified using XILINX ISE 14.2.

show abstract

Section: Resultsmentioning

confidence: 99%

Section: Resultsmentioning

confidence: 99%