Implementation of 4×4 2D Mesh NoC Architecture using FPGA

Majeed, Noor Dhyaa; Mahdi, Siraj Qays; Kadhim, Maha Abdulameer

doi:10.1109/bicits51482.2021.9509904

Cited by 2 publications

(2 citation statements)

References 10 publications

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“…Fig. 1 shows the NoC model based on the classic 2D-mesh structure [10,11]. In addition, some routing nodes and links can be removed from the regular network topology structure to form an irregular topology structure.…”

Section: Related Workmentioning

confidence: 99%

Design and Performance Analysis of Low Latency Routing Algorithm based NoC for MPSoC

Nagalaxmi¹,

Rao²,

Chandrasekhar³

2023

Int. j. commun. netw. inf. secur.

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The Network on Chip is appropriate where System-on-Chip technology is scalable and adaptable. The Network on Chip is a new communication architecture with a number of benefits, including scalability, flexibility, and reusability, for applications built on Multiprocessor System on a Chip (MPSoC). However, the design of efficient NoC fabric with high performance is critically complex because of its architectural parameters. Identifying a suitable scheduling algorithm to resolve arbitration among ports to obtain high-speed data transfer in the router is one of the most significant phases while designing a Network on chip based Multiprocessor System on a Chip. Low latency, throughput, space utilization, energy consumption, and reliability for Network on chip fabric are all determined by the router. The performance of the NoC system is hampered by the deadlock issues that plague conventional routing algorithms. This work develops a novel routing algorithm to address the deadlock problem. In this paper, a deterministic shortest path deadlock-free routing method is developed based on the analysis of the Turn Model. In the 2D-mesh structure, the algorithm uses separate routing methods for the odd and even columns. This minimizes the number of paths for a single channel, congestion, and latency. Two test scenarios—one with and one without a load test—were used to evaluate the proposed model. For a zero-load network, three clock cycles are utilized to transfer the packets. For the load network, five clocks are utilized to transfer the packets. The latency is measured for both cases without load and with load test and the corresponding latency is 3ns and 7ns respectively.The proposed method has an 18.57Mbps throughput. The area and power utilization for the proposed method are 69% (IO utilization) and 0.128W respectively. In order to validate the proposed method, the latency is compared with existing work and 50% latency is reduced both with and without congestion load.

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Section: Related Workmentioning

confidence: 99%

Design and Performance Analysis of Low Latency Routing Algorithm based NoC for MPSoC

Nagalaxmi¹,

Rao²,

Chandrasekhar³

2023

Int. j. commun. netw. inf. secur.

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“…The topology selected should be suitable for the outlines that are specified by the FPGA. The conditions of the topology that are to be concerned are listed in [19]. The successor of the next node shall always be a onedirectional link like a torus or a K-Ary 2 cube mesh or the torus topology.…”

Section: Introductionmentioning

confidence: 99%

Design and performance analysis of asynchronous network on chip for streaming data transmission on FPGA

Patil,

Sandi

2024

IJRES

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The majority of the system on chip (SoC) uses the network on chip (NoC) as routing ports for data transfer from node-to-node with minimal power consumption and low latency and high throughput. This paper concentrates on the ability to model the asynchronous NoCs on the asynchronous circuits on field programmable gate arrays (FPGAs). A 3×3 NoC and its universal asynchronous receiver transmitter (UART) protocol is designed and its simulation of the Verilog hardware description language (VHDL) code is done and tested on the Artix-7 FPGA kit, the testing processes in done using the Chipscope tool. In order to meet target requirements in terms of power consumption and latency, the label switching (LS) technique is used as routing. The proposed LS-NoC with level-encoded dual-rail (LEDR) encoding technique provides throughput by registering the packet between the different routers and it helps to improve throughput and speed. The effectiveness of the data transfer is measured and analyzed through a synthesis summary in terms of lookup table’s (LUT’s), slice registers, flip flops’s (FF’s), latency, and packet delivery ratio (PDR) for the traffic pattern generator. The proposed NoC is designed for 8×8 and each port size is 21 bits including ID’s of source and destination routers. The results can be justified by following results: improvement of LUTs is about 12%, flip-flops are 7%, improvement of throughput is 23% and delay is reduced by 26%.

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Implementation of 4×4 2D Mesh NoC Architecture using FPGA

Cited by 2 publications

References 10 publications

Design and Performance Analysis of Low Latency Routing Algorithm based NoC for MPSoC

Design and Performance Analysis of Low Latency Routing Algorithm based NoC for MPSoC

Design and performance analysis of asynchronous network on chip for streaming data transmission on FPGA

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