Implementation of a network flow lookup circuit for next-generation packet classifiers

A hardware acceleration scheme for memory-efficient flow processing

“…With the presence of QDRII SDRAMs, a hardware circuit proposed by Yang [11] is able to search packet headers against a 128K-entrant look up table at target line-rates. Based on the same concept, alternative memory architecture is presented in this paper to enable data lookup on large tables with several million entries.…”