Implementation of a neural network for digital pulse shape analysis on a FPGA for on-line identification of heavy ions

González-Jiménez, R.; Sánchez-Raya, M.; Gómez-Galán, Juan Antonio; Flores, J.L.; Dueñas, J. A.; Martel, I.

doi:10.1016/j.nima.2012.01.034

Cited by 19 publications

(12 citation statements)

References 8 publications

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“…This comparison indicates that the optimization of the parallel architecture has no benefit compared to other similar implementations in the literature. However, Figure 12 illustrates a comparison of the PF between our proposed serial architectures and those obtained in Ortigosa et al 15 and Jime´nez et al 16 This comparison indicates that our optimized series architecture offers the best PF. This comparison confirms the results obtained in the preceding paragraph using the Pc criterion.…”

Section: Performance Evaluationmentioning

confidence: 69%

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Architectural exploration of multilayer perceptron models for on-chip and real-time road sign classification

Faiedh

Hamdi

Bouguezzi

et al. 2018

Proceedings of the Institution of Mechanical Engineers, Part I:

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Road sign recognition is part of the automatic driver assistance systems implemented on the dashboard of vehicles. The recognition task is often carried out based on a classification procedure manipulating the detected signs. Classification tasks can be resolved by the use of multilayer artificial neural network systems. This article proposes an optimized real-time on-chip hardware implementation of multilayer perceptron system used for road sign classification. Four architectural approaches were described: on the one hand, the classic and the serial optimized architectures that offer a very significant reduction in hardware resources, and, on the other hand, the parallel and the optimized architectures, which offer a much reduced, time execution. In order to benefit from the advantages of the allocated hardware resources and the classification of the runtime process, these four architectures have been implemented on field programmable gate array Virtex-6 devices and their performances were quantified and evaluated according to a cost criterion. The energy dissipated by each of these architectures was measured; the achieved results have allowed us to conclude that the serial optimized architecture is the optimal solution, since it creates a tradeoff between the low cost, and the energy efficiency, and still real-time for the considered application.

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Section: Performance Evaluationmentioning

confidence: 69%

“…In the literature, two types of architectures of MLP are used: Serial architecture 15,16 uses a minimum area but requires a lot of time for execution due to the use of a single functional unit. Parallel architecture 15,17,18 allows a very rapid execution through the parallelisms of neurons but uses a very large area.…”

Section: Introductionmentioning

confidence: 99%

Architectural exploration of multilayer perceptron models for on-chip and real-time road sign classification

Faiedh

Hamdi

Bouguezzi

et al. 2018

Proceedings of the Institution of Mechanical Engineers, Part I:

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“…As shown the ADD and MULTIPLY operations are two main operating blocks which have important impacts on hardware resource utilization, operating frequency and power consumption. Furthermore, four dimensional (4-D) arrays of Hopfield neural network weights, described in (21), require many multipliers and adders for hardware implementation of (9) [25][26][27]. Implementation of (15) reduces the number of utilized resources that required in hardware implementation of HNN on FPGA.…”

Section: Neuron Architecturementioning

confidence: 99%

Hardware Description of Digital Hopfield Neural Networks for Solving Shortest Path Problem

Asgari¹,

Kavian

2014

NNW

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The shortest path problem is an important issue in communication networks which is used by many practical routing protocols. The aim of this paper is to present an intelligent model based on Hopfield neural networks (HNNs) for solving shortest path problem and implement that on Field Programmable Gate Arrays (FPGAs) chips. The Cyclone Π-EP2C70F896C6 FPGA chip from ALTERA Inc. is considered for hardware implementing and VHDL language is employed for hardware description. The synthesizing results show the proposed architecture of neuron is more efficient than relevant neuron model for chip area utilization and consequently improving the maximum operating frequency and power consumption. The proposed router core is employed to find shortest paths in ring, star and mesh communication networks and the results demonstrate the efficiency and superiority of proposed core.

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“…-higher than 99% accuracy is attained at around 1,000 keVee for the related problem of 12 C and 13 C ion identification, with each decision realised in 20 µs [29];…”

Section: Introductionmentioning

confidence: 98%

“…resilient BP [19], and scaled conjugate gradient [20]). Among the results reported in [21][22][23][24][25][26][27][28][29][30]:…”

Section: Introductionmentioning

confidence: 99%

Pulse Shape Discrimination of Neutrons and Gamma Rays Using Kohonen Artificial Neural Networks

Tambouratzis

Chernikova

Pzsit

2013

Journal of Artificial Intelligence and Soft Computing Research

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The potential of two Kohonen artificial neural networks I ANNs) - linear vector quantisa - tion (LVQ) and the self organising map (SOM) - is explored for pulse shape discrimination (PSD), i.e. for distinguishing between neutrons (n's) and gamma rays (γ’s). The effect that la) the energy level, and lb) the relative- of the training and lest sets, have on iden- tification accuracy is also evaluated on the given PSD datasel The two Kohonen ANNs demonstrate compfcmentary discrimination ability on the training and test sets: while the LVQ is consistently mote accurate on classifying the training set. the SOM exhibits higher n/γ identification rales when classifying new paltms regardless of the proportion of training and test set patterns at the different energy levels: the average tint: for decision making equals ∼100 /e in the cax of the LVQ and ∼450 μs in the case of the SOM.

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Implementation of a neural network for digital pulse shape analysis on a FPGA for on-line identification of heavy ions

Cited by 19 publications

References 8 publications

Architectural exploration of multilayer perceptron models for on-chip and real-time road sign classification

Architectural exploration of multilayer perceptron models for on-chip and real-time road sign classification

Hardware Description of Digital Hopfield Neural Networks for Solving Shortest Path Problem

Pulse Shape Discrimination of Neutrons and Gamma Rays Using Kohonen Artificial Neural Networks

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