Implementation of a Real-Time Spectrum Analyzer on FPGA Platforms

Iglesias, Victor; Grajal, Jesús; Sánchez, María del Carmen; López‐Vallejo, Marisa

doi:10.1109/tim.2014.2344411

Cited by 35 publications

(13 citation statements)

References 29 publications

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“…The second option is to calculate the spectrum of that portion of the spectrum using the FFT with the corresponding windowing for achieving the exact RBW setting. In both cases, it is still necessary to run through the frequency range that has been set on, which means that for spans larger than the IF bandwidth, several iterations of the acquisition are required [10], [11].…”

Section: A Real-time Analyzersmentioning

confidence: 99%

Waveform Approach for Assessing Conformity of CISPR 16-1-1 Measuring Receivers

Azpúrua

Pous

Oliva

et al. 2018

IEEE Trans. Instrum. Meas.

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Abstract-An alternative approach for assessing the conformity of electromagnetic interference measuring receivers with respect to the baseline CISPR 16-1-1 requirements is proposed. The method's core is based on the generation of digitally synthesized complex waveforms comprising multisine excitation signals and modulated pulses. The superposition of multiple narrowband reference signals populating the standard frequency bands allows for a single-stage evaluation of the receiver's voltage accuracy and frequency selectivity. Moreover, characterizing the response of the weighting detectors using modulated pulses is more repeatable and less restrictive than the conventional approach. This methodology significantly reduces the amount of time required to complete the verification of the receiver's baseline magnitudes, because time-domain measurements enable a broadband assessment while the typical calibration methodology follows the time-consuming narrow band frequency sweep scheme. Since the reference signals are generated using arbitrary waveform generators, they can be easily reproduced from a standard numerical vector. For different test receivers, the results of such assessment are presented in the 9 kHz-1 GHz frequency range. Finally, a discussion on the measurement uncertainty of this methodology for assessing measuring receivers is given.

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Section: A Real-time Analyzersmentioning

confidence: 99%

Waveform Approach for Assessing Conformity of CISPR 16-1-1 Measuring Receivers

Azpúrua

Pous

Oliva

et al. 2018

IEEE Trans. Instrum. Meas.

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show abstract

“…For example, a recent work in [13] has presented an FPGA-based architecture for managing ultrasonic beacons in a local positioning system. In [29], a real-time FPGA implementation of a spectrum analyzer is presented. The design and test of an FPGA-based radio detection and sensor signal acquisition/processing platform is presented in [30].…”

Section: Algorithms For Four Esc Tasks and Their Implementation Dementioning

confidence: 99%

An FPGA-Based Implementation of a Multifunction Environment Sensing Device for Shared Access With Rotating Radars

Khan

Lehtomäki

Hossain

et al. 2018

IEEE Trans. Instrum. Meas.

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To protect radar receivers and to facilitate shared access (SA) in radar bands, regulatory bodies have recommended the use of spectrum monitoring devices called environmental sensing capability (ESC). High-speed and low-cost ESC devices are required to process in real-time the large amount of data (IQ samples) for detection of radar signals and to differentiate them from secondary users (SUs) signals. In this paper, we present a Field Programmable Gate Array (FPGA) based design and implementation of a multifunction ESC device that can detect radar pulses and can also differentiate them from SU signals in microsecond time scales. The proposed ESC device performs the following tasks in parallel: 1) it detects and differentiates between radar and SU signals; 2) measures received signal strength (RSS) from SUs for radar protection; and 3) also measures SUs' airtime utilization (ATU) in a channel which can be used to perform load balancing (based on ATU) of SUs on different channels for efficient access. Detection of signals requires threshold setting. We present a novel minimum-based threshold setting technique which is suitable for real-time operation of energy detectors. We implement a prototype of the proposed ESC device design on a Wireless Open Access Research Platform node which is equipped with a Xilinx FPGA. We evaluate the performance of the implemented device and show that with very high probability (close to 100%) it detects and differentiates between radar and SU signals. Moreover, it also accurately measures the ATU of SUs.

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“…Thus, design of an efficient FFT processor is of great significance in meeting the requirements of real-time applications in terms of speed, accuracy, low cost, and a smaller chip area. The FFT algorithm is mainly implemented on field-programmable gate arrays (FPGAs) [10][11][12], which offer advantages such as higher performance, less design time, and lower costs than digital signal processor-based systems (DSPs) [13][14][15]. Moreover, the increasing gate density of FPGAs in recent years has enabled designers to implement data-parallel signal processing algorithms by using massively parallel architectures that can meet high-speed processing requirements; this has resulted in implementations on FPGA that deliver outstanding performance in many applications.…”

Section: Introductionmentioning

confidence: 99%

A Pipelined FFT Processor Using an Optimal Hybrid Rotation Scheme for Complex Multiplication: Design, FPGA Implementation and Analysis

et al. 2018

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Abstract:The fast Fourier transform (FFT) is the most prevalent algorithm for the spectral analysis of acoustic emission signals acquired at ultra-high sampling rates to monitor the condition of rotary machines. The complexity and cost of the associated hardware limit the use of FFT in real-time applications. In this paper, an efficient hardware architecture for FFT implementation is proposed based on the radix-2 decimation in frequency algorithm (R2DIF) and a feedback pipelined technique (FB) that allows effective sharing of storage between the input and output data at each stage of the FFT process via shift registers. The proposed design uses an optimal hybrid rotation scheme by combining the modified coordinate rotation digital computer (m-CORDIC) algorithm and a binary encoding technique based on canonical signed digit (CSD) for replacing the complex multipliers in FFT. The m-CORDIC algorithm, with an adaptive iterative monitoring process, improves the convergence of computation, whereas the CSD algorithm optimizes the multiplication of constants using a simple shift-add method. Therefore, the proposed design does not require the large memory typically entailed by existing designs to carry out twiddle factor multiplication in large-point FFT implementations, thereby reducing its area on the chip. Moreover, the proposed pipelined FFT processor uses only distributed logic resources and does not require expensive dedicated functional blocks. Experimental results show that the proposed design outperforms existing state-of-the-art approaches in speed by about 49% and in resource utilization by around 51%, while delivering the same accuracy and utilizing less chip area.

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Implementation of a Real-Time Spectrum Analyzer on FPGA Platforms

Cited by 35 publications

References 29 publications

Waveform Approach for Assessing Conformity of CISPR 16-1-1 Measuring Receivers

Waveform Approach for Assessing Conformity of CISPR 16-1-1 Measuring Receivers

An FPGA-Based Implementation of a Multifunction Environment Sensing Device for Shared Access With Rotating Radars

A Pipelined FFT Processor Using an Optimal Hybrid Rotation Scheme for Complex Multiplication: Design, FPGA Implementation and Analysis

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