Implementation of a reconfigurable ASIP for high throughput low power DFT/DCT/FIR engine

Abstract

In this article we present an ASIP design for a discrete fourier transform (DFT)/discrete cosine transform (DCT)/finite impulse response filters (FIR) engine. The engine is intended for use in an accelerator-chain implementation of wireless communication systems. The engine offers a very high degree of flexibility, accepting and accelerating performance approaches that of any-number DFT and inverse discrete fourier transform, one and two dimension DCT, and even general implementations of FIR equations. Performance approaches that of dedicated implementations of such algorithms. A customized yet flexible redundant memory map allows processor-like access while maintaining the pipeline full in a dedicated architecture-like manner. The engine is supported by a proprietary software tool that automatically sets the rounding pattern for the accelerator rounder to maintain a required signal to quantization noise or output RMS for any given algorithm. Programming of the processor is done through a mid-level language that combines register-specific instructions with DFT/DCT/FIR specificinstructions. Overall the engine allows users to program a very wide range of applications with software-like ease, while delivering performance very close to hardware. This puts the engine in an excellent spot in the current wireless communications environment with its profusion of multi-mode and emerging standards.

Design and implementation of application‐specific instruction‐set processor design for high‐throughput multi‐standard wireless orthogonal frequency division multiplexing baseband processor

“…FIFO interface). A detailed description of engine's instructions and programming can be found in [11, 13, 21].…”

A Reconfigurable Application-specific Instruction-set Processor for Fast Fourier Transform processing

“…In recent past many ASIPs were developed specialized for image and video processing [1], Viterbi or LDPC channel coding/decoding ( [2], [3]) and Fast Fourier Transform processing ( [4], [5]). Later, the idea of adding dynamically reconfigurable circuitry in the datapath of the processor got popular and rASIPs were made for Software-Defined Radio (SDR) applications [6] and also for basic Digital Signal Processing (DSP) applications [7]. To control the reconfigurable part of rASIPs, special instructions were added in the instruction-set of the processor and also necessary additional hardware for interfacing.…”

Application Specific Hardware Design Simulation for High Performance Embeddeed System

“…J. Qiu, X. Gao, Y. Jiang, X. Xiao [7] proposed a hybrid simulation framework which improves the previous simulation methods by aggressively utilizing the host machine resources. H. M. Hassan, K. Mohammed and A. F. Shalash [8] presented an ASIP design for a discrete Fourier transform (DFT)/discrete cosine transform (DCT)/finite impulse response filters (FIR) engine.…”