Implementation of AES algorithm on FPGA for low area consumption

Khose, Pritamkumar N.; Raut, Vrushali

doi:10.1109/pervasive.2015.7087102

Cited by 22 publications

(9 citation statements)

References 2 publications

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“…To implement the system with reduced processing speed, effective mechanisms are discussed in the paper and . The paper is integrating the system with the intrusion detection system. The paper has developed an algorithm which uses different hardware for the encryption and the decryption process.…”

Section: Resultsmentioning

confidence: 99%

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Screening the covert key using honey encryption to rule out the brute force attack of AES—a survey

.¹,

Renjith²,

Kumar³

2016

Security Comm Networks

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Recently, the major challenging attack is the side channel attack for both symmetric and asymmetric algorithm. Because in both cases, the secret key has to be sent out via a safe secured channel. The advanced encryption standard (AES) is mentioned as the best standard encryption algorithm by the US government, but there is one major attack on the AES that is the brute force attack. So, how to rule out these kinds of attack and how it is implemented effectively in hardware are being discussed in this paper. The honey encryption scheme is an effective algorithm, and it is also being discussed. In this paper, the detailed description of the AES and the methods to improve its speed and how it is integrated with the honey technique have been discussed. The different kinds of attacks and the various solutions are discussed for both of the algorithms. A survey of papers which has used these algorithms for various reasons with different perspective has been given. The honey algorithm creates the fake message for the wrong try of the key puncher. Thus, this is considered as the best algorithm, but it is also has some disadvantages that is also focussed in our survey. Copyright © 2017 John Wiley & Sons, Ltd.

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Section: Resultsmentioning

confidence: 99%

“…Khose et al proposed that a system of high speed with reduced area, low power, low cost, and standard throughput of data is achieved. The time taken for key generation is also reduced.…”

Section: System For Shaping Aes Algorithmmentioning

confidence: 99%

Screening the covert key using honey encryption to rule out the brute force attack of AES—a survey

.¹,

Renjith²,

Kumar³

2016

Security Comm Networks

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“…This design was implemented on Spartan-3, and it utilizes 150 slices at maximum operating frequency of 90 MHz. Khose and Raut [10] proposed implementation of AES algorithm on FPGA in order to achieve high speed of data processing and also to reduce time for generating key. This design utilizes 201 slices and 2 BRAMs at maximum operating frequency of 70 MHz.…”

Section: Literature Surveymentioning

confidence: 99%

High-Speed Area-Efficient Implementation of AES Algorithm on Reconfigurable Platform

Mulani¹,

Mane²

2020

Computer and Network Security

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Nowadays, digital information is very easy to process, but it allows unauthorized users to access to this information. To protect this information from unauthorized access, cryptography is one of the most powerful and commonly used techniques. There are various cryptographic algorithms out of which advanced encryption standard (AES) is one of the most frequently used symmetric key cryptographic algorithms. The main objective of this chapter is to implement fast, secure, and areaefficient AES algorithm on a reconfigurable platform. In this chapter, AES algorithm is designed using Xilinx system generator, implemented on Nexys-4 DDR FPGA development board and simulated using MATLAB Simulink. Synthesis results show that the implementation consumes 121 slice registers, and its maximum operating frequency is 1102.536 MHz. Throughput achieved by this implementation is 14.1125 Gbps.

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“…Thus, hardware implementation is very fast, and reliable compared to software implementations. Moreover, in long term it has lower costs by considering the requirement of software implementation to update occasionally between times [5]. The rest of the paper is organized as follows.…”

Section: Introductionmentioning

confidence: 99%

Loop Unrolling Implementation of an AES Algorithm using Xilinx System Generator

Al-Gailani¹,

Al-Khafaji²

2019

Iraqi Journal of ICT

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Cryptographic algorithm is a tool that is used to secure the transmitted data on the network. The current standard algorithm the Advanced Encryption Standard (AES) is used to maintain the security and reliability of the encrypted data whether these data are stored in computer or in transmit. AES can be implemented either in hardware or software, however hardware implementation is more sensible for high speed applications. In this paper, AES-128 algorithm is implemented in hardware in order to achieve a high-speed data processing. It is implemented on an FPGA platform using HLL language and Xilinx ISE software. The design is effectively optimized and Synthesizable with high accuracy using the conventional blocks of Xilinx System Generator. The results of implementation have enhanced the performance in terms of resource utilization, speed and power consumption as compared with other related works. The circuit operates at a maximum frequency of 800.000 MHz which offers a high throughput of 102.4 Gbps on virtex6 xc6vlx130t-3ff1156, in addition it occupies only 2,405 slices.

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Implementation of AES algorithm on FPGA for low area consumption

Cited by 22 publications

References 2 publications

Screening the covert key using honey encryption to rule out the brute force attack of AES—a survey

Screening the covert key using honey encryption to rule out the brute force attack of AES—a survey

High-Speed Area-Efficient Implementation of AES Algorithm on Reconfigurable Platform

Loop Unrolling Implementation of an AES Algorithm using Xilinx System Generator

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