2012
DOI: 10.1109/ted.2012.2197624
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Implementation of an a-Si:H TFT Gate Driver Using a Five-Transistor Integrated Approach

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Cited by 30 publications
(17 citation statements)
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“…As shown in Fig. 8 Table II compares the power consumption of the proposed circuit with those of recently described circuits using highfrequency pull-down schemes [9], [10]. Although a work with a lower bias for the pull-down TFTs and a smaller capacitive load of the driving clock signals, which is related mainly to the size of the pull-up TFT, has been achieved [9], the previously developed circuit still consumes a significant amount of power owning to its high-frequency pull-down operation.…”
Section: Resultsmentioning
confidence: 99%
See 1 more Smart Citation
“…As shown in Fig. 8 Table II compares the power consumption of the proposed circuit with those of recently described circuits using highfrequency pull-down schemes [9], [10]. Although a work with a lower bias for the pull-down TFTs and a smaller capacitive load of the driving clock signals, which is related mainly to the size of the pull-up TFT, has been achieved [9], the previously developed circuit still consumes a significant amount of power owning to its high-frequency pull-down operation.…”
Section: Resultsmentioning
confidence: 99%
“…Although a work with a lower bias for the pull-down TFTs and a smaller capacitive load of the driving clock signals, which is related mainly to the size of the pull-up TFT, has been achieved [9], the previously developed circuit still consumes a significant amount of power owning to its high-frequency pull-down operation. Moreover, one work [10] has an output swing of 31 V and uses the fewer components to reduce the total capacitive loads associated with the driving clock signals. However, the 6.25-kHz pull-down structure can be improved to reduce the power consumption even further.…”
Section: Resultsmentioning
confidence: 99%
“…Thus, T1 is turned on prior to T3 in the first and second SSCs. These two SSCs then experience successively the same pre-charge, pull-up, pull-down, and low level holding processes as described in [5], [7], and [8]. As a result, the gate driver outputs 1551-319X © 2014 IEEE.…”
Section: Proposed Gate Driver and Operationmentioning
confidence: 99%
“…By integrating scan driver with thin film transistors (TFTs) on the panel, the display systems can be cheaper and thinner [4][5][6]. However, there are some difficulties for MOTFTs to integrate the scan driver due to the considerable leakage current with the gate-source voltage as zero compared with a-Si:H TFTs or low-temperature poly-Si TFTs.…”
Section: Introductionmentioning
confidence: 99%