Implementation of application-specific DSP for OFDM systems

Lee, J.H.; Moon, Ji‐Yun; Heo, K.L.; Sunwoo, Myung Hoon; Oh, Sangchul; Kim, I.H.

doi:10.1109/iscas.2004.1328834

Cited by 27 publications

(13 citation statements)

References 4 publications

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“…Complexity results refer to gate and memory complexity in silicon for a 90 nm CMOS technology and standardcells library. The comparison includes an application-specific instruction set processor (ASIP) [23], two macrocells specifically designed for DVB-T (see [24,42]) and a macrocell obtained by an automatic IP generator [10]. Note that the proposed cascade macrocell stands for its low complexity while maintaining similar application [37], whose target is the real-time implementation of a 128-point 528-MSamples/s FFT.…”

Section: Implementation Results and Comparison With The State-of-the-artmentioning

confidence: 99%

Design and Comparison of FFT VLSI Architectures for SoC Telecom Applications with Different Flexibility, Speed and Complexity Trade-Offs

Saponara

Rovini

Fanucci

et al. 2011

Circuits Syst Signal Process

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The design of Fast Fourier Transform (FFT) integrated architectures for System-on-Chip (SoC) telecom applications is addressed in this paper. After reviewing the FFT processing requirements of wireless and wired Orthogonal Frequency Division Multiplexing (OFDM) standards, including the emerging Multiple Input Multiple Output (MIMO) and OFDM Access (OFDMA) schemes, three FFT architectures are proposed: a fully parallel, a pipelined cascade and an in-place variable-size architecture, which offer different trade-offs among flexibility, processing speed and complexity. Silicon implementation results and comparisons with the state-of-the-art prove that each macrocell outperforms the known works for a target application. The fully parallel is optimized for throughput requirements up to several GSamples/s enabling Ultra-wideband (UWB) communications by using all channels foreseen in the standard. The pipelined cascade macrocell minimizes complexity for large size FFTs sustaining throughput up to 100 MSamples/s. The in-place variable-size FFT macrocell stands for its flexibility by allowing run-time reconfigurability required in OFDMA schemes while attaining the required throughput to support MIMO communications. The three architectures are also compared with common case-studies and target technology

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Section: Implementation Results and Comparison With The State-of-the-artmentioning

confidence: 99%

Design and Comparison of FFT VLSI Architectures for SoC Telecom Applications with Different Flexibility, Speed and Complexity Trade-Offs

Saponara

Rovini

Fanucci

et al. 2011

Circuits Syst Signal Process

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show abstract

“…This section presents the overall architecture, new instructions and their hardware architectures to efficiently implement OFDM systems [20][21][22][23][24]. FFT can be classified into decimation-in-frequency (DIF) FFT and DIT FFT.…”

Section: New Instructions and Their Architecturementioning

confidence: 99%

SPOCS: Application Specific Signal Processor for OFDM Communication Systems

Baek

Kim

Sunwoo

2008

J Sign Process Syst Sign Image Video Technol

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This paper presents an Application-Specific Signal Processor (ASSP) for Orthogonal Frequency Division Multiplexing (OFDM) Communication Systems, called SPOCS. The instruction set and its architecture are specially designed for OFDM systems, such as Fast Fourier Transform (FFT), scrambling/descrambling, puncturing, convolutional encoding, interleaving/deinterleaving, etc. SPOCS employs the optimized Data Processing Unit (DPU) to support the proposed instructions and the FFT Address Generation Unit (FAGU) to automatically calculate input/output data addresses. In addition, the proposed Bit Manipulation Unit (BMU) supports efficient bit manipulation operations. SPOCS has been synthesized using the SEC 0.18 μm standard cell library and has a much smaller area than commercial DSP chips. SPOCS can reduce the number of clock cycles over 8% 53% for FFT and about 48%~84% for scrambling, convolutional encoding and interleaving compared with existing DSP chips. SPOCS can support various OFDM communication standards, such as Wireless Local Area Network (WLAN), Digital Audio Broadcasting (DAB), Digital Video Broadcasting-Terrestrial (DVB-T), etc.

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“…In the most recent panorama [1][2][3][4][5][6][7][8][9][10][11][12] of digital processing systems, the design of application specific instruction-set processors (ASIPs) is gaining ground to fill the gap between ASICs and DSPs. ASIPs are flexible within an application domain, being able to accomplish a group of functionalities using a set of common operations.…”

Section: Introductionmentioning

confidence: 99%

“…ASIPs are flexible within an application domain, being able to accomplish a group of functionalities using a set of common operations. ASIP designs have been proposed in literature for motion estimation [1,4], Viterbi or LDPC channel coding/decoding [2,3], GNSS receiver [6], Discrete Cosine Transform [8], Fast Fourier Transform [7,8], and cryptography [9]. Since they are optimized towards certain applications, ASIPs combine the high performance and efficiency of a dedicated solution with the flexibility of a programmable solution.…”

Section: Introductionmentioning

confidence: 99%

ASIP-based reconfigurable architectures for power-efficient and real-time image/video processing

Saponara

Casula

Fanucci

2008

J Real-Time Image Proc

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To meet both flexibility and performance requirements, particularly when implementing high-end real-time image/video processing algorithms, the paper proposes to combine the application specific instruction-set processor (ASIP) paradigm with the reconfigurable hardware one. As case studies, the design of partially reconfigurable ASIP (r-ASIP) architectures is presented for two classes of algorithms with widespread diffusion in image/video processing: motion estimation and retinex filtering. Design optimizations are addressed at both algorithmic and architectural levels. Special processor concepts used to trade-off performance versus flexibility and to enable new features of post-fabrication configurability are shown. Silicon implementation results are compared to known ASIC, DSP or reconfigurable designs; the proposed r-ASIPs stand for their better performance-flexibility figures in the respective algorithmic class

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Implementation of application-specific DSP for OFDM systems

Cited by 27 publications

References 4 publications

Design and Comparison of FFT VLSI Architectures for SoC Telecom Applications with Different Flexibility, Speed and Complexity Trade-Offs

Design and Comparison of FFT VLSI Architectures for SoC Telecom Applications with Different Flexibility, Speed and Complexity Trade-Offs

SPOCS: Application Specific Signal Processor for OFDM Communication Systems

ASIP-based reconfigurable architectures for power-efficient and real-time image/video processing

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