Implementation of cellular genetic algorithms on a CNN chip: Simulations and experimental results

Horváth, András; Rásonyi, Miklós

doi:10.1002/cta.1823

Cited by 3 publications

(3 citation statements)

References 21 publications

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“…Considering the circuits shown in Figure 5, the average discharge current can be calculated by incorporating the sub threshold leakage equation [9]. Equations (6), (7) and (8) give the average discharge current of the SIC, COSIC and CPSIC structures, respectively.…”

Section: Minimum Clock Pulse Frequencymentioning

confidence: 99%

“…Programmable vision sensors are effective in high‐speed applications which require all or part of the processing such as kernel convolution to be performed in‐pixel. DPS cell are also important for in situ digital processing vision sensors such as image compression imagers , CNN network chips and cellular logic networks . Although there have been different vision chips presented that can perform the processing using compact analog photodiode data , however, analog processing circuits usually lack accuracy since the current and voltage parameters usually change between 1 and 5% of the full swing value depending on the device geometry .…”

Section: Introductionmentioning

confidence: 99%

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Application of dynamic counter circuits in programmable digital pixel sensor architectures

Habibi

2013

Circuit Theory & Apps

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In this paper, a high dynamic range digital pixel sensor (DPS) is presented. Each pixel receives light illumination and converts the intensity level to a digital code. The analog‐to‐digital conversion is performed in‐pixel. The pixel structure incorporates light to pulse signal converter and compact in‐pixel dynamic counter to convert the pulse signal to binary coded data. Different variations of the custom design dynamic counters are analyzed in a 0.18 µm technology, and their application in the DPS is investigated. It is shown that due to the limited clock frequency required in the sensor pixel, the dynamic counter can be incorporated as a pulse to binary code converter. Performance specifications such as power consumption, dynamic range and resolution of the presented structure are investigated using a 100 × 100 pixel sensor. The presented sensor is an effective solution for use in digital field programmable smart image sensors and vision chips since the pixel output is a regular binary code while no global digital counter bus is required. The fill factor of the presented design remains close to that of typical DPSs. Copyright © 2013 John Wiley & Sons, Ltd.

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Section: Minimum Clock Pulse Frequencymentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Application of dynamic counter circuits in programmable digital pixel sensor architectures

Habibi

2013

Circuit Theory & Apps

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“…The fine-grained model is also one of the most popular parallel techniques. In [21,22], the finegrained parallel GAs were used. Individuals of this model are usually placed on a large 2D grid.…”

Section: Introductionmentioning

confidence: 99%

The Fine-Grained Parallel Micro-Genetic Algorithm and Its Application to Broadband Conical Corrugated-Horn Antenna

Chang¹,

Zhou²,

Chen³

et al. 2013

PIER

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Abstract-The fine-grained parallel micro-genetic algorithm (FGP-MGA) is developed to solve antenna design problems. The synthesis of uniformly exited unequally spaced array is presented. Comparison with the micro-genetic algorithm (MGA) has been carried out. It is seen that the FGPMGA significantly outperforms MGA, in terms of both the convergence rate and exploration ability. The FGPMGA can also reduce the optimization time. Then the FGPMGA and the body of revolution finite-difference time-domain (BOR-FDTD) are combined to achieve an automated design process for conical corrugated-horn antenna. Numerical simulation results show that the horn antenna has good impedance matching (the VSWR is less than 1.5), stable beamwidth and gain, as well as good rotation symmetry patterns over the whole band 8∼13 GHz.

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Lookup table‐based negative‐bias temperature instability effect and leakage power co‐optimization using genetic algorithm approach

Bhattacharjee

Sahu

Pradhan

2021

Circuit Theory & Apps

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SummaryAs a result of continuous scaling of transistors, negative bias temperature instability (NBTI) has become a serious reliability concern which causes the device to degrade over its lifetime. Similarly, leakage power also remains a key issue in deep submicron technologies. Both NBTI‐related delay degradation and standby time leakage power depend strongly on the circuit's input patterns. The input vector control (IVC) technique can be used for mitigating both NBTI‐related delay degradation and leakage power. However, the input vectors with the least NBTI‐induced degradation may not be the same ones with the least leakage power in any circuit; therefore, co‐optimization is needed to minimize leakage and NBTI‐induced degradation. In this paper, a genetic algorithm (GA)‐based approach is presented to co‐optimize both NBTI‐related performance degradation and also leakage power. We are also presenting a trade‐off analysis by giving different weightage to the NBTI effect and leakage power. Simulation results applied on ISCAS'85 benchmark circuits illustrate that on average our proposed technique saves up to 21.85% and 17.68% circuit performance degradation and the leakage power, respectively.

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Implementation of cellular genetic algorithms on a CNN chip: Simulations and experimental results

Cited by 3 publications

References 21 publications

Application of dynamic counter circuits in programmable digital pixel sensor architectures

Application of dynamic counter circuits in programmable digital pixel sensor architectures

The Fine-Grained Parallel Micro-Genetic Algorithm and Its Application to Broadband Conical Corrugated-Horn Antenna

Lookup table‐based negative‐bias temperature instability effect and leakage power co‐optimization using genetic algorithm approach

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