Implementation of computation-reduced DCT using a novel method

Abstract

The discrete cosine transform (DCT) performs a very important role in the application of lossy compression for representing the pixel values of an image using lesser number of coefficients. Recently, many algorithms have been devised to compute DCT. In the initial stage of image compression, the image is generally subdivided into smaller subblocks, and these subblocks are converted into DCT coefficients. In this paper, we present a novel DCT architecture that reduces the power consumption by decreasing the computational complexity based on the correlation between two successive rows. The unwanted forward DCT computations in each 8 × 8 sub-image are eliminated, thereby making a significant reduction of forward DCT computation for the whole image. This algorithm is verified with various high-and less-correlated images, and the result shows that image quality is not much affected when only the most significant 4 bits per pixel are considered for row comparison. The proposed architecture is synthesized using Cadence SoC Encounter® with TSMC 180 nm standard cell library. This architecture consumes 1.257 mW power instead of 8.027 mW when the pixels of two rows have very less difference. The experimental result shows that the proposed DCT architecture reduces the average power consumption by 50.02 % and the total processing time by 61.4 % for high-correlated images. For less-correlated images, the reduction in power consumption and the total processing time is 23.63 and 35 %, respectively.

High Efficient Reconfigurable and Self Testable Architecture for Sensor Node

“…Security is essential for the application, for example, battlefield, environmental observation, and smart home to be executed. To ensure the data security of WSN, it is important to recognize nodes [21][22]. In any case, it is a test for the nodes to run encryption calculations and store information because of the restricted computational capacity and resources.…”

“…Compare to the Rivest-Shamir-Adleman (RSA), Advanced Encryption Standards (AES) takes lesser time and gives better security than Secure Hash Algorithms (SHA) [20]. To reduce the power consumption altering the data path is suggested several multipliers reduced in [22]. To prove the hardware efficiency the architecture can be implemented in a field-programmable gate array [23].…”