Implementation of Convolutional Neural Networks in Memristor Crossbar Arrays with Binary Activation and Weight Quantization

Abstract

We propose a hardware-friendly architecture of a convolutional neural network using a 32 × 32 memristor crossbar array having an overshoot suppression layer. The gradual switching characteristics in both set and reset operations enable the implementation of a 3-bit multilevel operation in a whole array that can be utilized as 16 kernels. Moreover, a binary activation function mapped to the read voltage and ground is introduced to evaluate the result of training with a boundary of 0.5 and its estimated gradient. Additionally, we adopt a fixed kernel method, where inputs are sequentially applied to a crossbar array with a differential memristor pair scheme, reducing unused cell waste. The binary activation has robust characteristics against device state variations, and a neuron circuit is experimentally demonstrated on a customized breadboard. Thanks to the analogue switching characteristics of the memristor device, the accurate vector−matrix multiplication (VMM) operations can be experimentally demonstrated by combining sequential inputs and the weights obtained through tuning operations in the crossbar array. In addition, the feature images extracted by VMM during the hardware inference operations on 100 test samples are classified, and the classification performance by off-chip training is compared with the software results. Finally, inference results depending on the tolerance are statistically verified through several tuning cycles.

New-Style Logic Operation and Neuromorphic Computing Enabled by Optoelectronic Artificial Synapses in an MXene/Y:HfO2 Ferroelectric Memristor

“…Previous researchers have developed a series of memristor devices imbued with logic functions that trigger diverse logic operations by configuring distinct thresholds to induce varied states in the logic devices. Although new logic devices manifest different logic functions contingent upon temperature, humidity, and lighting conditions, they typically necessitate multiple devices as input units to execute logic truth tables predicated on alterations in conductivity. − …”

Neuron Circuit Based on a Split-gate Transistor with Nonvolatile Memory for Homeostatic Functions of Biological Neurons

“…Recently, research has focused on integrating neuromorphic systems and hard-warebased neural networks with various emerging memory devices to enable energy-efficient operation of artificial intelligence algorithms [9,10,. For instance, on-chip learning can reduce power consumption and compensate for the degradation caused by device Recently, research has focused on integrating neuromorphic systems and hard-warebased neural networks with various emerging memory devices to enable energy-efficient operation of artificial intelligence algorithms [9,10,. For instance, on-chip learning can reduce power consumption and compensate for the degradation caused by device variation [44][45][46][47][48][49].…”

“…Recently, artificial neural networks (ANNs), inspired by the brain, have been actively researched and developed [ 1 ]. Particular attention has been paid to spiking neural net-works (SNNs) that utilize biological spike timing–dependent plasticity (STDP) rules to function as event-driven systems for unsupervised learning [ 2 , 3 , 4 , 5 , 6 , 7 , 8 , 9 , 10 ]. Since such SNNs pursue a more bio-plausible direction than other ANNs do, it is necessary to explore the signal transmission mechanisms of biological neurons and synapses to gain a deeper understanding of these SNNs.…”

Memristor Crossbar Array with Enhanced Device Yield for In-Memory Vector–Matrix Multiplication

“…Memristor has been extensively studied as a potential candidate for next-generation storage-class memory devices and artificial synaptic devices. − Typically, the memristor has a metal–insulator–metal structure for resistive switching behaviors and requires an initial electroforming process. Once formed, the device can operate, with the resistance state switching between the low-resistance state (LRS) and high-resistance state (HRS) through set and reset operations, respectively.…”