2020
DOI: 10.1007/s10470-020-01638-5
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Implementation of deep neural networks on FPGA-CPU platform using Xilinx SDSOC

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Cited by 15 publications
(9 citation statements)
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“…This memory is the main reason for the sluggishness and the weakness in the time complexity of FO-based algorithm. However, the sluggishness and weakness in time complexity would be acceptable for the following reasons: i) The rapid development of implementing a very speed CPUs for data processing could be used in implementing FO-based algorithms for numerous applications [18,21,46]; ii) Many applications have a sample time that is adequate with algorithms depending on FO calculus, for example the power systems [4], the temperature control systems [50,76], and electro-mechanical systems [56]. Moreover, to simplify the computation complexity of the proposed FOPID-FOAC algorithm, the numerical solution of the fractional order differential equation in Eq.…”
Section: Scenario 3: Uncertainty Suppressionmentioning
confidence: 99%
“…This memory is the main reason for the sluggishness and the weakness in the time complexity of FO-based algorithm. However, the sluggishness and weakness in time complexity would be acceptable for the following reasons: i) The rapid development of implementing a very speed CPUs for data processing could be used in implementing FO-based algorithms for numerous applications [18,21,46]; ii) Many applications have a sample time that is adequate with algorithms depending on FO calculus, for example the power systems [4], the temperature control systems [50,76], and electro-mechanical systems [56]. Moreover, to simplify the computation complexity of the proposed FOPID-FOAC algorithm, the numerical solution of the fractional order differential equation in Eq.…”
Section: Scenario 3: Uncertainty Suppressionmentioning
confidence: 99%
“…Hassan et al [8] presented a HW/SW co-design implementation of AlexNet on an FPGA. They performed the first layer of AlexNet on hardware and achieved 2147483647 clock cycles, which would be approximately 10.7 ms when considering a frequency of 0.2 GHz.…”
Section: Comparisons To Related Workmentioning
confidence: 99%
“…Besides the high-level synthesis (HLS) tool that can compile deep learning C/C++ code for programmable logic in the hardware [251], Xilinx also developed The Deep Learning Processor Unit (DPU) intellectual property (IP) core that can be integrated into the programmable logic of selected Zynq-7000 SoC and Zynq UltraScale+ MPSoC devices with direct connections to the processing system. Specifically, this DPU is a programmable engine dedicated to convolutional neural networks.…”
Section: A Deep Learning Processor Unit (Dpu)mentioning
confidence: 99%