Implementation of Dormand-Prince based chaotic oscillator designs in different IQ-Math number standards on FPGA

Koyuncu, İ̇smail; Şeker, Halil İbrahim

doi:10.16984/saufenbilder.505497

Cited by 6 publications

(6 citation statements)

References 33 publications

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“…The Eq. 3 presents equation of the DP numeric algorithm [43]. Expressions that contain the derivative of a function as unknown are called differential equations.…”

Section: Dormand-prince Algorithm and Sprott-jafari Chaotic Systemmentioning

confidence: 99%

A Novel Dormand-Prince Based Hybrid Chaotic True Random Number Generator on FPGA

Koyuncu

Şeker²,

Alçın

et al. 2021

Balkan Journal of Electrical and Computer Engineering

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This study presents a Dormand-Prince-based hybrid chaotic True Random Number Generator Design (TRNG) that can be used for secure communication and cryptographic applications on Field Programmable Gate Array (FPGA). In this design, a chaotic oscillator unit has been implemented with an FPGA-based Sprott-Jafari chaotic oscillator model suitable with IQ-Math fixed point number and IEEE 754-1985 floating point number standards. Random numbers have been produced with the quantization of the results generated by the chaotic oscillator. XOR has been performed with FPGA-based ring oscillator structure on the post-processing unit so as to enhance the randomness. The differential equation of the chaotic system used in the TRNG design was modelled using Dormand-Prince numerical algorithm method. The design on FPGA has been realized in two separate number formats including 32-bit (16I-16Q) IQ-Math fixed point number standard and 32-bit IEEE 754-1985 floating point number standard. The realized design has been coded in VHDL, a hardware description language, and the Xilinx ISE 14.7 program has been used for the system design. The TRNG design has been synthesized and tested for the Virtex-6 (XC6VLX240T-1FF1156) FPGA chip. The maximum operating frequencies of the TRNG in 32-bit IQ-Math fixed point number standard and 32-bit IEEE 754-1985 floating point number standard reach 344.585 MHz and 316 MHz, respectively. The throughputs of the TRNG in 32-bit IQ-Math fixed point number standard and 32-bit IEEE 754-1985 floating point number standard have been obtained as 344 Mbit/s and 316 Mbit/s, respectively. 1 Mbit sequence has been generated by using TRNG system. Randomness analysis of the generated numbers has been

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“…The Eq. 3 presents equation of the DP numeric algorithm [43]. Expressions that contain the derivative of a function as unknown are called differential equations.…”

Section: Dormand-prince Algorithm and Sprott-jafari Chaotic Systemmentioning

confidence: 99%

A Novel Dormand-Prince Based Hybrid Chaotic True Random Number Generator on FPGA

Koyuncu

Şeker²,

Alçın

et al. 2021

Balkan Journal of Electrical and Computer Engineering

Self Cite

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“…Chaotic and hyperchaotic oscillators have been active topics for research during the last years due to its usefulness in the development of chaotic secure communication systems and other applications that have been implemented using either analog or digital electronics, as already shown in [23]. In recent years, great efforts have been carried out on the development of chaos-based true random number generator (TRNG) structures due to the features ( [24]- [26]) including noise-like properties and hiding the information signal of chaotic oscillators ( [27]- [29]). Random number generators have been used in many areas including cryptography, applications using the Monte-Carlo method, computer simulations and modeling and numerical analysis applications ( [30]- [33]).…”

Section: Introductionmentioning

confidence: 99%

A 5-D Multi-Stable Hyperchaotic Two-Disk Dynamo System With No Equilibrium Point: Circuit Design, FPGA Realization and Applications to TRNGs and Image Encryption

Vaidyanathan

Sambas²,

Abd-El-Atty

et al. 2021

IEEE Access

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In this work, we devise a new 5-D hyperchaotic dynamo system by adding two feedback controllers to the Rikitake 2-disk dynamo system (1958). We show that the new 5-D hyperchaotic system does not possess any equilibrium point and deduce that the new 5-D system has a hidden hyperchaotic attractor. Using Multisim, we develop an electronic circuit design of the new 5-D hyperchaotic dynamo system for practical applications. We also exhibit the implementation of the new 5-D hyperchaotic dynamo system by using a field-programmable gate array (FPGA), which requires adders, subtractors and multipliers. The hardware resources are given for the application of three numerical methods, all of them providing results in good agreement with MATLAB simulations. As an application, we devise a dual core high speed hybrid true random number generator (TRNG) using Ring and Heun algorithm based on the new 5-D hyperchaotic oscillator on FPGA. Based on the hyperchaotic features of the proposed 5-D hyperchaotic dynamo system, we suggest a new encryption approach for colour images. Simulation outcomes of the presented encryption approach confirm that our chaotic system has good cryptographic properties and its usability in different cryptographic purposes.

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“…For this purpose, Euler, Heun, 4th order Runge-Kutta, Runge-Kutta-Butcher and Dormand-Prince are the numerical algorithms used in the literature [28,35,36]. Among these algorithms, the algorithm that can show the most characteristic of the CSs and produce the closest results is the Dormand-Prince (DP) algorithm [37,38].…”

Section: Introductionmentioning

confidence: 99%

“…Rajagopal et al [33] designed a new 3-D chaotic system on FPGA using Runge-Kutta Butcher (RK5B) numerical algorithm in 32-bit IEEE-754-1985 floating point number format. Koyuncu et al [37] designed the SEA chaotic oscillator as 16I-16Q, 14I-14Q, 12I-12Q, 10I_10Q, 8I-8Q fixed point based on FPGA using DP numerical algorithm and obtained the operating frequencies of the systems in the range of 344-366 MHz. Seker et al [36] carried out the DP numerical algorithm-based design of the chaotic oscillator on FPGA in 32-bit IEEE-754-1985 floating point number format and present the operating frequency of the design as 316 MHz.…”

Section: Introductionmentioning

confidence: 99%

“…Kizmaz et al [40] carried out the designs and chaos analysis of Memristor-Based Simplest Chaotic system based on DP numerical algorithm in their study. Koyuncu et al [41] performed the Dormand-Prince based chaotic oscillator design with golden proportion balance point on FPGA. In this study, SPCO chaotic system was designed on Xilinx Virtex-7 FPGA using DP numerical algorithm in 32-bit IEEE 754-1985 floating point number format.…”

Section: Introductionmentioning

confidence: 99%

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CCII current conveyor and dormand-prince-based chaotic oscillator designs for secure communication applications

Alçın

Tuna

Pehlivan

et al. 2020

International Advanced Researches and Engineering Journal

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Chaos is one of the important research areas in recent years. The chaotic signal generator is one of the most basic structure in the chaos-based researches and applications. In this study, Sundarapandian-Pehlivan Chaotic Oscillator (SPCO) designs have been implemented in 2 different platforms as analog-based using Second-Generation Current Controlled Current Conveyor (CCII) and FPGA-based with one of the chaotic oscillator that has been presented to the literature namely Sundarapandian-Pehlivan system. The structure used for the design of CCII-based chaotic oscillator and the results obtained from the study have been presented. In the second phase, the design of SPCO has been realized in order to utilize for running in FPGA chips using Dormand-Prince (DP) numeric algorithm. The design has been coded in VHDL using 32-bit IEEE-754-1985 floating point representation. The designed system has been tested by synthesizing it in Xilinx ISE Design Tools program. Then, the test results obtained from DPbased SPCO structure have been presented. In the last phase, the designed system has been synthesized for VIRTEX-7 FPGA. FPGA chip resource consumption values that obtained after the Place-Route process are presented. According to the results, the maximum operating frequency of DP-based SPCO unit on FPGA is obtained as 362.608 MHz. In future studies, the designs of Pseudo Random Number Generator (RNG) and True RNG can be performed using DP-based SPCO unit implemented successfully in this study.

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Implementation of Dormand-Prince based chaotic oscillator designs in different IQ-Math number standards on FPGA

Cited by 6 publications

References 33 publications

A Novel Dormand-Prince Based Hybrid Chaotic True Random Number Generator on FPGA

A Novel Dormand-Prince Based Hybrid Chaotic True Random Number Generator on FPGA

A 5-D Multi-Stable Hyperchaotic Two-Disk Dynamo System With No Equilibrium Point: Circuit Design, FPGA Realization and Applications to TRNGs and Image Encryption

CCII current conveyor and dormand-prince-based chaotic oscillator designs for secure communication applications

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