Implementation of encoder and decoder for LDPC codes based on FPGA

Cheng, Kwang-Ting; Shen, Qi; Liao, Sheng-Kai; Peng, Cheng-Zhi

doi:10.21629/jsee.2019.04.02

Cited by 16 publications

(4 citation statements)

References 7 publications

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“…Figure 3(b) shows that 62% of the CPU time is spent on memory access (49% for the data read and 13% for the data write), 36% for instructions, and only 2% for memory access out of the cache memory. Te higher percentage of access memory can be justifed by the separated processing of (1) Initialize all m c i ⟶ v j � 0, m v j ⟶ c i � L(0) v j and Itermax (2) for i � 1 to Itermax do Horizontal processing (C2V computation): (3) for each check node c i (4) for each variable node v j connected to c i (5) Calculate min 1 & min 2 (6) end for line 4 (7) for each variable node v j connected to c i (8)…”

Section: Results Of the Profling Analysismentioning

confidence: 99%

“…Te frst one is hardware based on application-specifc integrated circuits (ASICs) or feld-programmable gate array (FPGA) circuits. Tis approach not only achieves low latency and high throughput [6][7][8][9] but also brings a high development cost. Tis is a limitation for applications requiring fast time-to-market or for technologies with multiple and fast-evolving standards.…”

Section: Introductionmentioning

confidence: 99%

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Embedded Parallel Implementation of LDPC Decoder for Ultra-Reliable Low-Latency Communications

Benhayoun,

Razi,

Mansouri

et al. 2023

Applied Computational Intelligence and Soft Computing

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Ultra-reliable low-latency communications, URLLC, are designed for applications such as self-driving cars and telesurgery requiring a response in milliseconds and are very sensitive to transmission errors. To match the computational complexity of LDPC decoding algorithms to URLLC applications on IoT devices having very limited computational resources, this paper presents a new parallel and low-latency software implementation of the LDPC decoder. First, a decoding algorithm optimization and a compact data structure are proposed. Next, a parallel software implementation is performed on ARM multicore platforms in order to evaluate the latency of the proposed optimization. The synthesis results highlight a reduction in the memory size requirement by 50% and a three-time speedup in terms of processing time when compared to previous software decoder implementations. The reached decoding latency on the parallel processing platform is 150 μs for 288 bits with a bit error ratio of 3.410–9.

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Section: Results Of the Profling Analysismentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Embedded Parallel Implementation of LDPC Decoder for Ultra-Reliable Low-Latency Communications

Benhayoun,

Razi,

Mansouri

et al. 2023

Applied Computational Intelligence and Soft Computing

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“…Further strategies to enhance LDPC encoding and decoding techniques were proposed in subsequent studies [38][39][40]. One such investigation proposed a high-throughput IR-QC-LDPC encoding and decoding method that utilized a normalized min-sum algorithm (NMSA), achieving a decoding throughput of 27.85 Mbps when implemented on an FPGA.…”

Section: Related Workmentioning

confidence: 99%

Enhancing Data Communication Performance: A Comprehensive Review and Evaluation of LDPC Decoder Architectures

Subhi,

Al-Doori,

Alani

2023

ISI

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Error Correction Codes (ECCs) stand as a linchpin in ensuring data accuracy in wireless communication. As the landscape of modern communication standards continues to expand, there is a mounting inclination towards efficient ECC technologies, such as Low-Density Parity-Check codes (LDPCs). Distinguished by their near-capacity performance and low computational complexity, LDPCs are increasingly utilized in the successful encoding and decoding of data. This study undertakes an exploration of recent advancements in LDPC research, encompassing the analysis of decoding algorithms, architectures, applications, simulations, real-world implementations, and complexities across various hardware platforms. The central research problem addressed within this work is the identification of the most efficacious LDPC decoder implementation, with an emphasis placed on Field-Programmable Gate Array (FPGA) technology. From the outcomes of this study, the Min-Sum algorithm emerged as the favored choice for LDPC decoding, particularly within FPGA implementations. The selection of this algorithm is attributable to its simplicity and implementation feasibility, thus directly addressing the posed research problem. The inherent simplicity of the Min-Sum algorithm's structure renders it a practical choice for real-world applications. Further, its proficiency in error correction and compatibility with FPGA hardware underscore its potential for augmenting the reliability of data transmission in communication systems. The findings of this study advocate for the Min-Sum algorithm as a valuable asset in LDPC decoding, notably within FPGA implementations. This positions it as a promising candidate for optimizing data communication systems. The selection of FPGA as the implementation platform reaffirms its practicality and relevance in contemporary communication technology, thus offering a comprehensive solution to the identified research problem.

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“…It developed and tested a prototype 5G mm-wave large multiple input multiple output (MIMO) antenna using standard PCB techniques. It works in the 5G spectrum and is quite selective [12].…”

Section: Introductionmentioning

confidence: 99%

Security-based low-density parity check encoder for 5G communication

Rajangam,

Alagarsamy,

Radhakrishnan

et al. 2024

Bulletin EEI

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The fifth generation (5G) of mobile telecommunication standards is intended to offer better performance and efficiency. One of the most significant difficulties in delivering safe data transfer through the transmission channel in the emerging 5G technology is channel-coding security. This research primarily focused on offering information transmission that is secure in the place of novel assaults such as side-channel attacks. In this research, we present a low-density parity check (LDPC) encoder that is constructed using the multiplicative masking method to overcome side-channel attacks, one of the most significant security concerns for the upcoming 5G system. As a result, it offers greater security, reduced complexity, and higher performance. Power, area, and delay can all be calculated using LDPC codes. Comparing multiplicative masking implemented LDPC encoders to ordinary channel coding techniques in terms of security seen that multiplicative masking implemented LDPC encoders offer more security. The program Xilinx ISE 14.7 can synthesize the analysis. The advantage of multiplicative masking is that it offers a promising level of security through the principle of randomization, which is the foundation of the procedure. According to the analysis, the secured transmission of the data by the proposed multiplicative masking implemented LDPC encoder is increased.

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Implementation of encoder and decoder for LDPC codes based on FPGA

Cited by 16 publications

References 7 publications

Embedded Parallel Implementation of LDPC Decoder for Ultra-Reliable Low-Latency Communications

Embedded Parallel Implementation of LDPC Decoder for Ultra-Reliable Low-Latency Communications

Enhancing Data Communication Performance: A Comprehensive Review and Evaluation of LDPC Decoder Architectures

Security-based low-density parity check encoder for 5G communication

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