Implementation of EPON Systems Supporting Accurate Time Synchronization

Abstract

In this paper factors affecting accuracy of time synchronization in EPON are analysed and the scheme of time synchronization in EPON based on IEEE1588v2 protocol is designed and implemented by FPGA. Experimental result shows that the scheme is feasible and good time synchronization accuracy about 20 nanoseconds can be reached.When access networks are applied as backhaul networks from cell site to mobile switching center, time synchronization is usually required to be provided [1] [2]. Ethernet Passive Optical Network (EPON), as a suitable backhaul from cell site to mobile switching center, doesn't have an inborn accurate time synchronization scheme.There have been studies [3][4] about clock synchronization schemes, but implementing a low-cost accurate time synchronization scheme still cause great interest to people. In order to support accurate time synchronization in EPON, we propose a scheme based on a precision time protocol known as IEEE1588v2. We analyze several factors which affect time synchronization performance, such as dynamic bandwidth allocation and message transmission interval. We designed an EPON system based on FPGA including IEEE1588v2 function modules and prove that the time synchronization scheme is feasible and good time synchronization accuracy about 20 nanoseconds can be reached through experiment. II. The time synchronization schemeIn order to achieve a low-cost accurate time synchronization scheme in EPON, we propose an idea of supporting a precision time protocol as IEEE1588v2 through a special service with high quality of service (QOS) requirement which is processed in OLT and ONU's hardware. We use Master and Slave to stand for the function modules in OLT and ONU which deal with clock management, generate and process the packets used by IEEE1588v2 protocol. The Master gets its real time clock from a parent clock reference and the Slave delivers its synchronized clock from Master's clock to wireless nodes connected to it through certain interfaces, such as 1PPS. The scheme is shown in Fig. 1. Fig.1. the time synchronization scheme In order to analyze the factors which affect the time accuracy, an IEEE1588v2 interaction process is shown in Fig. 2. At first the Master transmits the sync message and at 2 s T the Slave receives the message. Then the Master transmits a follow up message indicating the exact transmitting time 1 m T of the sync message. At 3 s T the Slave sends out a Delay-Req message to the Master and the time of receipt is 4 m T . Then the Master transmits a Delay-Req response message indicating 4 m T and the Slave receives it at 6 s T . The formulas computing difference between the Master and Slave's clocks could be obtained as follows: 2 1 _ s m T T O ffs e t M S D e la y − = + (1) 4 3 _ m s T T O ffse t S M D ela y − = − + (2) Where Offset stands for the time difference between the master and slave, MS_Delay stands for the line delay from the master to the slave and SM_Delay stands for the line delay from the slave to the master. Here we assume the MS_Delay and SM_Delay ar...