Implementation of high speed processor for computing convolution sum for DSP applications

Abstract

In this paper, we report on transistor level (ASIC) implementation of high speed processor for the first time, for computing convolution sum (linear and circular) of two sequences. The convolution sum was calculated through the orientation of the sequences into array formation for parallel processing, owing towards high speed architecture design. The architectures were implemented and functionality was verified through spice simulator. The mathematical transformation along with binary coded decimal(BCD) arithmetic have been incorporated for the practical implementation of convolution sum, ensure substantial reduction of propagation delay in comparison with earlier reported architectures. The performance parameters such as propagation delay, dynamic switching power consumption were calculated through spice using 90nm CMOS technology. The propagation delay of the resulting 4-point linear convolution was only ~12.79ns and consumes ~27.56mW power with a layout area of ~9.06mm 2 . Moreover, performance parameters of 4-point circular convolution were ~14.8ns propagation delay with ~37.8mW switching power consumption.