Implementation of High Throughput XTS-SM4 Module for Data Storage Devices

Liang, Zheng; Li, Changting; Liu, Zongbin; Zhang, Lingchen; Ma, Cunqing

doi:10.1007/978-3-030-01704-0_15

Cited by 4 publications

(6 citation statements)

References 9 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The authors in Reference [17] proposed a fully unrolled pipeline to adapt SM4 to the high throughput requirement in the XTS‐SM4 module architecture. The area of the S‐box is optimised, and the quantity of registers is controlled as well.…”

Section: Related Workmentioning

confidence: 99%

“…To summarise, the existing research work on the SM4 cipher concerned with optimising the area, such as in Reference [7], improving the throughput, such as in References [8,17], or optimising both the area and throughput, such as in References [11][12][13][14]. However, all these studies did not focus on optimising the power/energy consumption, which is the dominant issue in RCDs, and it is more important than utilising the area [2].…”

Section: Related Workmentioning

confidence: 99%

“…Many researchers have focused on optimising the SM4 cipher for achieving low area use [7,[9][10][11][12][13][14][15][16]. Others have concentrated on implementing high throughput designs [8,[11][12][13][14][16][17][18]. Some authors have optimised the SM4 cipher for achieving low power consumption [19,20].…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Performance evaluation of the SM4 cipher based on field‐programmable gate array implementation

Abed

Jaffal

Mohd

et al. 2021

IET Circuits, Devices & Syst

View full text Add to dashboard Cite

Information security is essential to ensure security of exchanged sensitive data in resource‐constrained devices (RCDs) because they are used widely in the Internet of things (IoT). The implementation of special ciphers is required in these RCDs, as they have many limitations and constraints, such as low power/energy dissipation, and require low hardware resources. The SM4 cipher is one of the common block ciphers, which can be easily implemented and offers a high level of security. The objective of this study is to determine the optimum field‐programmable gate array (FPGA) design for SM4 to facilitate reconfiguring the FPGA with an optimum design during operation. Various FPGA design options for SM4 ciphers are examined, and the performance metrics are modeled: power, energy, area, and speed. Scalar and pipelined designs with one or multiple hardware rounds are considered without altering the cipher algorithm. The results show that the best scalar implementation utilises less resources than the pipelined implementations by 7%. Alternatively, pipelined implementations perform better regarding speed and energy dissipation by 10 times and 40% of the scalar implementation, respectively. The pipeline implementations with eight or 16 rounds are optimum for continuous streams of data, and the two‐round design is the optimum design across ciphers.

show abstract

Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

See 1 more Smart Citation

Performance evaluation of the SM4 cipher based on field‐programmable gate array implementation

Abed

Jaffal

Mohd

et al. 2021

IET Circuits, Devices & Syst

View full text Add to dashboard Cite

show abstract

“…The execution of the High Throughput XTS‐SM4 Module for Data Storage Devices was demonstrated by Zheng et al 22 The main intention of this approach was adapting SM4 to high throughput requirements. Throughput and power consumption were the measures that were employed in this approach.…”

Section: Recent Related Work: a Reviewmentioning

confidence: 99%

Enhanced moth flame optimization based Supervision Kernel Entropy Component Analysis for high‐speed encrypted transmission model

Babu¹,

Kumar²

2021

Int J Communication

View full text Add to dashboard Cite

show abstract

“…Many related works have studied hardware architecture of SM4, but all of them are limited to a single operation mode. For example, references [5][6][7][8][9][10] only implemented the ECB mode, references [11][12] only implemented the CBC mode, reference [13]only implemented the CTR mode, and reference [14] only implemented the XTS mode. Different from existing works, a low-cost multi-mode hardware architecture of the SM4 algorithm is proposed to provide both flexibility and confidentiality.…”

Section: Introductionmentioning

confidence: 99%

Improving the Performance of Multi-Mode SM4 Block Cipher

Hu¹,

Chen²

2019

Int J Performability Eng

View full text Add to dashboard Cite

In this paper, a low-cost multi-mode hardware architecture is proposed for data confidentiality of resource-constrained IoT (Internet of things) devices. The proposed architecture adopts resource sharing technologies to reduce the number of s-boxes, eliminate memory requirement of expanded keys, and realize flexible reconfigurability of various operation modes. The FPGA implementation results show that only 1,326 LUTs and 1,000 registers are needed at 50MHz. Compared with related works, resource costs are reduced significantly.

show abstract

Implementation of High Throughput XTS-SM4 Module for Data Storage Devices

Cited by 4 publications

References 9 publications

Performance evaluation of the SM4 cipher based on field‐programmable gate array implementation

Performance evaluation of the SM4 cipher based on field‐programmable gate array implementation

Enhanced moth flame optimization based Supervision Kernel Entropy Component Analysis for high‐speed encrypted transmission model

Improving the Performance of Multi-Mode SM4 Block Cipher

Contact Info

Product

Resources

About