2012
DOI: 10.1049/iet-cta.2010.0739
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Implementation of linear model predictive control using a field-programmable gate array

Abstract: The paper investigates the design of a field programmable gate array based custom computer architecture solution for implementing model predictive control. The solution employs a primal logarithmic-barrier interior-point algorithm in order to handle actuator constraints. The solution also incorporates practical aspects of a control algorithm including state observation and data sampling. The resulting circuit is profiled by application to a disturbance rejection control problem of a 14'th order lightly damped … Show more

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Cited by 13 publications
(16 citation statements)
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“…Compared with [5], our TSA-based linear solver is ∼ 12× faster though no resource consumption results are available for comparison of area. From the power consumption perspective, actual processing utilization for our TSA-based SA design is low when compared to a 1D SA design.…”
Section: B Implementation Resultsmentioning
confidence: 99%
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“…Compared with [5], our TSA-based linear solver is ∼ 12× faster though no resource consumption results are available for comparison of area. From the power consumption perspective, actual processing utilization for our TSA-based SA design is low when compared to a 1D SA design.…”
Section: B Implementation Resultsmentioning
confidence: 99%
“…Our proposed design implements signed fixed-point number format with 9 integer bits and 8 binary bits, similar to [5], however our design differs in being wordlength and matrix size parameterizable at the PE level within the SA architecture. We make use of the DSP Blocks' dynamic configurability [6] to support multiple operations on the same hardware in different steps.…”
Section: A System Setupmentioning
confidence: 99%
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“…Whilst [14] presents a full fixed-point implementation, no analysis or guarantees are provided for handling the large dynamic range manifested in interior-point methods. Recently, activeset [18] and interior-point [16], [19] architectures were proposed using (very) reduced precision floating-point arithmetic and solving a condensed QP. Feasibility was demonstrated on an experimental setup with a 14th order SISO open-loop stable vibrating beam, with impressive computation times.…”
Section: A Background and Motivationmentioning
confidence: 99%
“…This issue becomes particularly important when one tries to implement MPC on special purpose hardware, such as FPGA's [21,28], PLC's [32,19,45] or PAC's [18]. For these devices, linear MPC is demanding, as they have limited memory space and very low processing power.…”
Section: Introductionmentioning
confidence: 99%