Implementation of low power FFT structure using a method based on conditionally coded blocks

Multicoding Techniqe to Reduce Power Dissipation in VLSIA Review

“…A bus may consist of set of parallel lines with repeaters between them. Butterfly structure of FFT is design is genrated and using of Canonic Sign Digit and Banary Coded Canonic Sign Digit was coded [7].…”

“…The capacitance of interconnect can be classified as coupling capacitance and self capacitance. The coupling capacitance is the capacitance between the adjacent data lines while the self capacitance refers to the capacitance between the substrate and the wire itself [7].The dynamic power in VLSI chip decides the behavior of chip and is highly dependent on the load capacitance and the coupling capacitance i.e. bus line signal transitions [6].…”