Implementation of MAC using area efficient and reduced delay vedic multiplier targeted at FPGA architectures

Abstract

The Multiply-Accumulator (MAC) unit always lies in the critical path that determines the speed of the overall hardware systems. Therefore, a high-speed MAC that is capable of supporting multiple precisions and parallel operations is highly desirable. This paper describes the implementation of a MAC unit using area efficient Vedic multiplier which enhanced in terms of area and path delay. Speed of the multiplier is very important to any Digital Signal Processors (DSPs). To construct a NxN bit Vedic Multiplier, four N/2xN/2 VM and three N-bit Ripple Carry Adders (RCAs) are required. But in our proposed VM, instead of 3 N-bit RCA, only one N-bit RCA and our two proposed adders are used. In our proposed Adders, the area required for N-bit RCA has been reduced, leading to a greater reduction in the logic delay. We have developed the generalized architectures for NxN VM, MAC unit and for our proposed Adders. The proposed MAC and conventional MAC are coded in Verilog, synthesized and simulated using ISE simulator. It is implemented on the Xilinx Spartan6 family xc6slx150t-4fgg900 FPGA. The Area and logic delay of the proposed MAC and conventional VM are compared.

FPGA implementation of efficient vedic multiplier

“…Here, input a=6 (00000110) and input b=-7 (11111001) and obtained 16 bit result for same is -42 (1111111111010110) which is displayed on LCD as shown in Figure 13. In Table I, the combinational path delay, for signed Vedic multiplier implemented in [6] and proposed signed Vedic multiplier using carry select adder is shown and compared, it can be clearly observed that the combinational path delay for signed Vedic multiplier using carry select adder is less as compared with existing signed Vedic multiplier, along with this the result is also compared with conventional booth multiplier as seen in table I. Hence proving the effectiveness of proposed work.…”

“…The main limitations in the method proposed in [6] are, i) to calculate the final result of multiplication, the authors have used 3 adders, in which adder 1 is ripple carry adder, and other 2 adders are combination of half adder and full adder, hence the delay involved is more for calculation of final product. ii) Other than this, q0 of Figure 2 is passing to the adder 2 in existing method, which is also affecting delay of multiplier.…”

“…Signed multiplier is proposed in [6] and performance is compared with conventional Booth multiplier. One of the major limitation as discussed in [6] is high delay in multiplier block, which has been improved in this work.…”

Design and Implementation of High Speed 64-Bit Multiply and Accumulator Unit Using FPGA

“…The conventional and proposed MAC unit is coded on verilog-HDL and XILINX ISE simulator. [5] The simulation on Spartan-3e family using XILINX ISE tool and coding on verilog. The result of delay is proposed multiplier is 41.562 ns and binary multiplier is 94.087.…”

“…This two 4-bit input multiplier first 2bit input multiplication by vertical and crosswise we start with LSB to MSB input multiplication and then addition of multiplication and to generated carry in previous one addition we added with next addition. [5] D.Design of 16x16 Bit Multiplier : This fig.6 to representation of block diagram of 16x16bit vedic multiplier using adder. Here two input given to 16-bit and we get the 32bit output data.…”