Implementation of (Normalised) RLS Lattice on Virtex

ACM Trans. Embed. Comput. Syst.

Schier

Gregg

2010

Adaptive filters are widely used in many applications of digital signal processing. Digital communications and digital video broadcasting are just two examples. Traditionally, small embedded systems have employed the least computationally intensive filter adaptive algorithms, such as normalized least mean squares (NLMS). This article shows that FPGA devices are a highly suitable platform for more computationally intensive adaptive algorithms. We present an optimized core which implements GSFAP. GSFAP is an algorithm with far superior adaptation properties than NLMS, and with only slightly higher computational complexity. To further optimize resource requirements we use logarithmic arithmetic, rather than conventional floating point, within the custom core. Our design makes effective use of the pipelined logarithmic addition units, and takes advantage of the very low cost of logarithmic multiplication and division. The resulting GSFAP core can be clocked at more than 80MHz on a one million-gate Xilinx XC2V1000-4 device. The core can be used to implement adaptive filters of orders 20 to 1000 performing echo cancellation on speech signals at a sampling rate exceeding 50kHz. For comparison, we implemented a similar NLMS core and found that although it is slightly smaller than the GSFAP core and allows a higher signal sampling rate for the corresponding filter orders, the GSFAP core has adaptation properties that are much superior to NLMS, and that our core can provide very sophisticated adaptive filtering capabilities for resource-constrained embedded systems.

Section: Related Workmentioning

confidence: 56%

GSFAP adaptive filtering using log arithmetic for resource-constrained embedded systems

ACM Trans. Embed. Comput. Syst.

Schier

Gregg

2010

“…For the order probability evaluation, POW and SQRT operations are also required. The 19-bit Logarithmic Number System (LNS) arithmetic [14,15] has been identified as the most convenient alternative for the RLS lattice filter implementation in our previous work [8,9].…”

Section: Lattice Filter Hw Designmentioning

confidence: 99%

“…Used RLS solution builds on the results presented in [13,8], where exponential forgetting is employed into the RLS lattice. This RLS lattice implementation with exponential forgetting can be extended by maintaining hypotheses about the necessary order using (1) and (2).…”

Section: Rls Lattice Algorithm With Order Probability Evaluationmentioning

confidence: 99%

See 1 more Smart Citation

RLS Lattice Algorithm with Order Probability Evaluation as an Accelerator for the Microblaze Processor

Pohl

2007 International Conference on Field Programmable Logic and Applications

2007

A high performance RLS lattice filter with evaluation of an unknown order of identified system was implemented as an accelerator PCORE for Xilinx EDK. The accelerator hardware can fully exploit parallelisms in the algorithm and remove load from a microprocessor. The EDK integration allows effective programing and debugging of a hardware accelerated DSP applications. The optimal logarithmic number system implementation of the RLS lattice IP core was used. Additionally, the extension by the order probability evaluation was implemented. Then, the core was wrapped in the System Generator. Finally, the generated EDK PCORE was modified to independent clock operation. Implemented solution makes possible evaluation of the RLS lattice filter of order 256 at 8 kHz input data rate in the best case. At the same time the order probability can be maintained. The implementation outperforms software solution up to 74 times and it is also performing 40% faster than other known solutions.

“…The implementation of the LSL filter with error-feedback [16][17][18] has proven good numerical behavior. In [16], it was shown that the filter can be efficiently implemented in field programmable gate arrays (FPGA). In the following text, this algorithm is referred to as the RLS lattice.…”

Section: Introductionmentioning

confidence: 99%

Implementation of the Least-Squares Lattice with Order and Forgetting Factor Estimation for FPGA

Pohl

EURASIP J. Adv. Signal Process.

Kadlec

2008

Self Cite

A high performance RLS lattice filter with the estimation of an unknown order and forgetting factor of identified system was developed and implemented as a PCORE coprocessor for Xilinx EDK. The coprocessor implemented in FPGA hardware can fully exploit parallelisms in the algorithm and remove load from a microprocessor. The EDK integration allows effective programming and debugging of hardware accelerated DSP applications. The RLS lattice core extended by the order and forgetting factor estimation was implemented using the logarithmic numbers system (LNS) arithmetic. An optimal mapping of the RLS lattice onto the LNS arithmetic units found by the cyclic scheduling was used. The schedule allows us to run four independent filters in parallel on one arithmetic macro set. The coprocessor containing the RLS lattice core is highly configurable. It allows to exploit the modular structure of the RLS lattice filter and construct the pipelined serial connection of filters for even higher performance. It also allows to run independent parallel filters on the same input with different forgetting factors in order to estimate which order and exponential forgetting factor better describe the observed data. The FPGA coprocessor implementation presented in the paper is able to evaluate the RLS lattice filter of order 504 at 12 kHz input data sampling rate. For the filter of order up to 20, the probability of order and forgetting factor hypotheses can be continually estimated. It has been demonstrated that the implemented coprocessor accelerates the Microblaze solution up to 20 times. It has also been shown that the coprocessor performs up to 2.5 times faster than highly optimized solution using 50 MIPS SHARC DSP processor, while the Microblaze is capable of performing another tasks concurrently.