Implementation of sum of absolute difference using optimized partial summation term reduction

Shah, Nehal N.; Agarwal, Khyati R.; Singapuri, Harikrishna

doi:10.1109/icaes.2013.6659390

Cited by 8 publications

(4 citation statements)

References 8 publications

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“…Register48 is centre point (0, 0) of the BMA and in 48 × 48 search area it is located at the centre of the search area, i.e. at position (16,16). When data is stored into register from memory, first it is permuted according to the selected format.…”

Section: Storing Data Into Registersmentioning

confidence: 99%

“…The hardware circuit based on adder and MUX for absolute difference calculation [13] is quicker compared with circuit presented in [14, 15]. On the basis of review, it is decided to use absolute difference calculator of [13] and PSTR [16]‐based multi‐operand adder, for execution of SAD between macroblock and CMBs in single clock cycle.…”

Section: Proposed Architecture Of Sad Processor With Parallel Memory mentioning

confidence: 99%

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Register array‐based sum of absolute difference processor with parallel memory system for fast motion estimation

Shah¹,

Dalal²

2018

IET Computers & Digital Techniques

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Fast search block matching algorithm (BMA)-based video coding provides reasonable good quality video with minute cost of computation. In fast BMA, clock cycles required to read pixel data are quite more compared with matching operation due to erratic location of candidate macroblocks (CMBs). With aim of reduction in number of clock cycles, parallel memory system is used in this study, which can accelerate reading of CMBs and speedup motion vector (MV) computation. Novel concept of register array is introduced to organise CMBs, which expedite computation hungry search process. Owing to shape of register array, lesser space is needed to store CMBs and architecture addresses wide range of search patterns. The proposed sum of absolute difference processor with parallel memory system computes MV of 1 macroblock in 28 clock cycles in average case. Compared to single memory system, it saves 68% and 80% clock cycles in CMB access of initial search and intermediate search process, respectively. Hardware architecture is tested with Xilinx Virtex5 field programmable gate array. The proposed fixed 8×8 macroblock size architecture processes 354 high definition (HD) (1080p) frames per second (fps) and configurable architecture processes 201 HD fps which is more than adequate for real-time encoding.

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Section: Storing Data Into Registersmentioning

confidence: 99%

Section: Proposed Architecture Of Sad Processor With Parallel Memory mentioning

confidence: 99%

Register array‐based sum of absolute difference processor with parallel memory system for fast motion estimation

Shah¹,

Dalal²

2018

IET Computers & Digital Techniques

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“…The architecture is divided into multiple stages, namely, absolute difference calculation (ADC), addition of absolute difference, and generation of 41 SAD combinations. To compute absolute difference, multiplexer Journal of Electrical and Computer Engineering 5 based ADC presented in [10] and, for addition of operands, adder presented in [11] Table 2. At very next, that is, on 17th clock, the remaining 25 combinations are computed.…”

Section: Macroblock Scanning Pattern and Vbsme Architecturesmentioning

confidence: 99%

Hardware Efficient Architecture with Variable Block Size for Motion Estimation

Shah¹,

Singapuri

Dalal

2016

Journal of Electrical and Computer Engineering

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Video coding standards such as MPEG-x and H.26x incorporate variable block size motion estimation (VBSME) which is highly time consuming and extremely complex from hardware implementation perspective due to huge computation. In this paper, we have discussed basic aspects of video coding and studied and compared existing architectures for VBSME. Various architectures with different pixel scanning pattern give a variety of performance results for motion vector (MV) generation, showing tradeoff between macroblock processed per second and resource requirement for computation. Aim of this paper is to design VBSME architecture which utilizes optimal resources to minimize chip area and offer adequate frame processing rate for real time implementation. Speed of computation can be improved by accessing 16 pixels of base macroblock of size 4 × 4 in single clock cycle using z scanning pattern. Widely adopted cost function for hardware implementation known as sum of absolute differences (SAD) is used for VBSME architecture with multiplexer based absolute difference calculator and partial summation term reduction (PSTR) based multioperand adders. Device utilization of proposed implementation is only 22k gates and it can process 179 HD (1920 × 1080) resolution frames in best case and 47 HD resolution frames in worst case per second. Due to such higher throughput design is well suitable for real time implementation.

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“…In our system, we used the sum of absolute difference (SAD) algorithm [8] that compares the previous and current frame to detect movement as shown in figure 6. If the difference between the consecutive frames is greater than threshold value, movement is detected.…”

Section: ) Movement Directionmentioning

confidence: 99%

Design and implementation of FPGA based automatic lecture recording system

Ahmad

Yang

Shahzad

et al. 2015

2015 17th International Conference on Advanced Communication Technology (ICACT)

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Tele-teaching and distance-learning concept is getting much consideration these days since it poses easy access and availability of well-known instructors' lectures and presentations. In relation to video lectures, one of the utmost important concerns is professional video recording. Video recording inside lecture halls requires experienced camera-work professionals, who can record video lecture in an eye-catching way that keep the viewer concentration. To eliminate the overhead of expensive camera-work professionals, recently, image recognition algorithms combined with camera controllers make automatic lecture recording possible. In this article, we present real time implementation of the field programmable gate arrays (FPGA) based automatic lecture recording system. The system comprises of FPGA board, which can take input from analog and/or digital video camera, the ARM processor unit, and camera mounted stepper motor. Real time Image recognition algorithms are used to detect the region of interest (ROI) boundaries, instructor's face, and instructor's movement direction. The stepper motor rotates the mounted camera as directed by the FPGA controller to follow the lecturer and board. Further, the proposed system is designed in a compatible manner that can take input from a variety of video formats. Successful video lecture recording at Hanyang University lecture hall validated the performance of the system.

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Implementation of sum of absolute difference using optimized partial summation term reduction

Cited by 8 publications

References 8 publications

Register array‐based sum of absolute difference processor with parallel memory system for fast motion estimation

Register array‐based sum of absolute difference processor with parallel memory system for fast motion estimation

Hardware Efficient Architecture with Variable Block Size for Motion Estimation

Design and implementation of FPGA based automatic lecture recording system

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