Implementation on FPGA Area-Delay Efficient Architecture of CSLA

Abstract

ABSTRACT:In the design of VLSI, area and delay is play important role and the field of VLSI less delay and low area is required adder unit in data processing processor for performing fast arithmetic operation. Architecture of CSLA, there is chance to reduce area & delay which is based on sum generation unit and carry generation unit. In this paper 128bit, 64bit, 32bit, 16bit conventional CSLA, modified CSLA and Proposed CSLA architecture have been implemented on FPGA and compared result in term area that is of count of gate and delay. The proposed design has reduced area and delay. This work has showed the performance of the proposed design in term of delay and area. ISim simulator is used for simulating the CSLA and synthesized using Xilinx ISE design suit 14.7 then implementation is done on in virtex7 FPGA kit.