Implementation Oriented Two-Sample Phase Locked Loop for Single-Phase PFCs

Abstract

A low-resource-consuming digital implementation of the Two-Sample (2S) Phase Locked Loop (PLL) for low cost single-phase Power Factor Correction (PFC) converters is proposed. The design replaces trigonometric functions with an oscillator and divisions with approximations, without reducing the 2S-PLL synchronization capability. The proposal is evaluated and validated by simulation and experimentally.